# US 8,785,901 B2 · Semiconductor devices having metal oxide patterns

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- Number: US 8,785,901 B2
- Document ID: US8785901B2
- Status: Granted
- Kind: B2
- Application number: 13/875,731
- Filed: 2013-05-02
- Published: 2013-09-19
- Granted: 2014-07-22
- Earliest claimed: 2009-03-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Junho Jeong; Sukhun Choi; Jangeun Lee; Kyunghyun Kim; Sechung Oh; Kyungtae Nam
- Web page: https://patentgrep.com/patent/US8785901B2

## CPC

- H10D 1/47: Resistors having no potential barriers
- H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD}
- H10N 70/026: {by physical vapor deposition, e.g. sputtering}
- H10N 70/041: {Modification of switching materials after formation, e.g. doping (shaping H10N70/061)}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 50/01: Manufacture or treatment
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.

## Claims

### Claim 1

A semiconductor device comprising:
a dielectric layer on a substrate;
a metal pattern in the dielectric layer;
a conductive metal-containing pattern on the metal pattern, the conductive metal-containing pattern including a same metal as the metal pattern and having a planarized top surface being coplanar with a top surface of the dielectric layer; and
a variable resistor on the conductive metal-containing pattern and electrically connected to the conductive metal-containing pattern,
wherein the conductive metal-containing pattern comprises a conductive metal oxide pattern adjacent to the metal pattern and an upper metal pattern on the conductive metal oxide pattern; and
wherein an oxygen concentration of the conductive metal oxide pattern is higher than an oxygen concentration of the upper metal pattern.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the upper metal pattern further comprises nitrogen.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the variable resistor directly contacts the planarized top surface of the conductive metal-containing pattern.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a barrier pattern between the dielectric layer and the metal pattern.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the dielectric layer comprises:
a dielectric interlayer surrounding a sidewall of a lower portion of the conductive metal-containing pattern and a sidewall of the metal pattern; and
a capping dielectric layer surrounding a sidewall of an upper portion of the conductive metal-containing pattern,
wherein the capping dielectric layer covers the barrier pattern.

### Claim 6 (depends on 1)

The semiconductor device of claim 1:
wherein the variable resistor changes into a plurality of resistance states having different associated resistivities; and
wherein a resistivity of the conductive metal-containing pattern is lower than a lowest among the resistivities of the resistance states.

### Claim 7

A semiconductor device comprising:
a dielectric layer on a substrate;
a metal pattern in the dielectric layer;
a conductive metal-containing pattern on the metal pattern, the conductive metal-containing pattern including a same metal as the metal pattern and having a planarized top surface being coplanar with a top surface of the dielectric layer;
a variable resistor on the conductive metal-containing pattern and electrically connected to the conductive metal-containing pattern; and
an amorphous lower electrode between the top surface of the conductive metal-containing pattern and the variable resistor.

### Claim 8

A semiconductor device comprising:
a dielectric layer on a substrate;
a first metal pattern in the dielectric layer;
a second metal pattern on the first metal pattern, the second metal pattern including a same metal as the first metal pattern, and having a planarized top surface being coplanar with the a surface of the dielectric layer; and
a variable resistor on the second metal pattern and electrically connected to the second metal pattern,
wherein a grain size of the second metal pattern is smaller than a grain size of the first metal pattern.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the second metal pattern further comprises nitrogen.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the second metal pattern further comprises oxygen.