# US 8,785,900 B2 · Resistive memory and methods of processing resistive memory

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- Number: US 8,785,900 B2
- Document ID: US8785900B2
- Status: Granted
- Kind: B2
- Application number: 13/619,106
- Filed: 2012-09-14
- Published: 2013-01-10
- Granted: 2014-07-22
- Earliest claimed: 2010-05-10
- Assignees: Micron Technology, Inc.
- Applicants: David H. Wells
- Inventors: David H. Wells
- Web page: https://patentgrep.com/patent/US8785900B2

## CPC

- H10N 70/8413: {adapted for resistive heating}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

## Claims

### Claim 1

A resistive memory cell, comprising:
a bottom electrode directly connected to an access device;
a resistive memory cell material on the bottom electrode;
a top electrode on the resistive memory cell material, wherein;
the top electrode is a heater electrode; and
the top electrode is self-aligned to the resistive memory cell material;
a metal spacer on the resistive memory cell material and adjacent a sidewall of the top electrode; and
a dielectric spacer on the resistive memory cell material and adjacent a sidewall of the metal spacer.

### Claim 2 (depends on 1)

The resistive memory cell of claim 1, wherein a width of the top electrode is smaller than a width of the bottom electrode.

### Claim 3 (depends on 1)

The resistive memory cell of claim 1, wherein the top electrode has a width of approximately 100 Angstroms.

### Claim 4 (depends on 1)

The resistive memory cell of claim 1, wherein the top electrode includes titanium nitride.

### Claim 5 (depends on 1)

The resistive memory cell of claim 1, wherein the top electrode includes tungsten.

### Claim 6 (depends on 1)

The resistive memory cell of claim 1, wherein the top electrode is not directly connected to the access device.

### Claim 7

A memory device, comprising:
an array of memory cells, wherein a number of the memory cells include:
an electrode directly connected to an access device;
a phase change random access memory (PCRAM) cell material on the electrode;
a heater electrode on the PCRAM cell material, wherein the heater electrode is self-aligned to the PCRAM cell material;
a metal spacer on the PCRAM cell material and adjacent a sidewall of the heater electrode; and
a dielectric spacer on the PCRAM cell material and adjacent a sidewall of the metal spacer.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein a first number of memory cells in the array are stacked on a second number of memory cells in the array.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the first number of memory cells and second number of memory cells are coupled to a common data line.