# US 8,785,328 B2 · Mask pattern for hole patterning and method for fabricating semiconductor device using the same

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- Number: US 8,785,328 B2
- Document ID: US8785328B2
- Status: Granted
- Kind: B2
- Application number: 13/607,898
- Filed: 2012-09-10
- Published: 2013-12-19
- Granted: 2014-07-22
- Earliest claimed: 2012-06-15
- Assignees: SK hynix Inc.
- Applicants: Jun-Hyeub Sun; Sung-Kwon Lee; Sang-Oh Lee
- Inventors: Jun-Hyeub Sun; Sung-Kwon Lee; Sang-Oh Lee
- Web page: https://patentgrep.com/patent/US8785328B2

## CPC

- H10P 72/0418: {for etching}
- G03F 1/00: Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/485: {Bit line contacts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
forming an etching target layer over a substrate including a first region and a second region;
forming a hard mask layer over the etching target layer;
forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns;
forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region;
removing the sacrificial spacer layer;
forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and
forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns as an etch mask.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the forming of the second etch mask comprises:
forming a planarization layer over the first etch mask;
forming a plurality of sacrificial line patterns over the planarization layer in a direction crossing with the line patterns;
forming a spacer layer over an entire surface of a structure including the sacrificial line patterns;
selectively etching the spacer layer and forming spacer patterns on sidewalls of the sacrificial line patterns;
removing the sacrificial line patterns; and
forming the mesh type pattern and the blocking pattern by etching the planarization layer using the spacer patterns as an etch mask.

### Claim 3 (depends on 2)

The method according to claim 2,
wherein, in the forming of the plurality of sacrificial line patterns, a plurality of sacrificial line patterns formed in the first region have a first spacing, and a plurality of sacrificial line patterns formed in the second region have a second spacing, and
wherein the second spacing is narrower than the first spacing.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the spacer layer gap-fills the second spacing.

### Claim 5 (depends on 2)

The method according to claim 2, wherein the spacer layer comprises an oxide layer.

### Claim 6 (depends on 2)

The method according to claim 2, wherein the etching of the planarization layer is performed until etching is stopped at a surface of the sacrificial spacer layer.

### Claim 7 (depends on 1)

The method according to claim 1, wherein, in the forming of the second etch mask, the mesh type pattern comprises a plurality of first lines formed between the line patterns and a plurality of second lines contacting the first lines and extending in a direction crossing with the line patterns.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the sacrificial spacer layer is formed as an oxide layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the line patterns and the mesh type pattern are formed as a spin-on carbon layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the first region comprises a cell matrix region and the second region comprises an edge region of the cell matrix region.

### Claim 11

A method for fabricating a semiconductor device, comprising:
forming an etching target layer over a substrate including a first region and a second region;
forming a hard mask layer over the etching target layer;
forming a first etch mask including a plurality of first line patterns alternately disposed with a plurality of second line patterns over the hard mask layer;
forming a second etch mask over the first etch mask, wherein the second etch mask includes a plurality of third line patterns extending in a direction crossing with the first and second line patterns and a blocking pattern covering the second region;
forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and
forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns as an etch mask.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the forming of the second etch mask comprises:
forming a planarization layer over the first etch mask;
forming a plurality of sacrificial line patterns over the planarization layer in a direction crossing with the line patterns;
forming a spacer layer over an entire surface of a structure including the sacrificial line patterns;
selectively etching the spacer layer and forming spacer patterns on sidewalls of the sacrificial line patterns;
removing the sacrificial line patterns; and
forming the third line patterns and the blocking pattern by etching the planarization layer using the spacer patterns as an etch mask.

### Claim 13 (depends on 12)

The method according to claim 12,
wherein, in the forming of the plurality of sacrificial line patterns, a plurality of sacrificial line patterns formed in the first region have a first spacing and a plurality of sacrificial line patterns formed in the second region have a second spacing, and
wherein the second spacing is narrower than the first spacing.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the spacer layer gap-fills the second spacing.

### Claim 15 (depends on 12)

The method according to claim 12, wherein the spacer layer comprises an oxide layer.

### Claim 16 (depends on 11)

The method according to claim 11, wherein the first line patterns, the third line patterns and the blocking pattern are each formed as a spin-on carbon layer and the second line patterns are formed as a polysilicon layer.

### Claim 17 (depends on 11)

The method according to claim 11, wherein the forming of the first etch mask including a plurality of first line patterns and a plurality of second line patterns comprises:
forming the plurality of first line patterns using a spin-on carbon layer over the hard mask layer;
forming a sacrificial spacer layer over the first line patterns;
gap-filling a polysilicon layer over the sacrificial spacer layer;
forming the second line patterns by etching back the polysilicon layer; and
removing the sacrificial spacer layer between the first line patterns and the second line patterns.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the sacrificial spacer layer comprises an oxide layer.

### Claim 19 (depends on 11)

The method according to claim 11, wherein the first region comprises a cell matrix region and the second region comprises an edge region of the cell matrix region.