# US 8,785,325 B2 · Method of manufacturing semiconductor device

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- Number: US 8,785,325 B2
- Document ID: US8785325B2
- Status: Granted
- Kind: B2
- Application number: 13/233,379
- Filed: 2011-09-15
- Published: 2012-08-16
- Granted: 2014-07-22
- Earliest claimed: 2011-02-14
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Gaku Sudo
- Inventors: Gaku Sudo
- Web page: https://patentgrep.com/patent/US8785325B2

## CPC

- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10N 50/01: Manufacture or treatment
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming first and second cores on a processed material;
forming a covering material having a stacked layer comprising first and second layers, the covering material covering an upper surface and a side surface of each of the first and second cores;
removing the second layer covering the first core;
forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material to expose a surface of the processed material;
removing the first and second cores; and
forming first and second patterns having a first width W1 and a second width W2 in parallel by etching the processed material in condition of using the first and second sidewall masks.

### Claim 2 (depends on 1)

The method of claim 1,
wherein the width W1 of the first sidewall mask is 1 F and the second width W2 of the second sidewall mask is 1 F<W2<2 F, where 2 F is a minimum processing size by photolithography.

### Claim 3 (depends on 1)

The method of claim 1,
wherein the width W1 of the first sidewall mask is 1 F and the second width W2 of the second sidewall mask is 2 F≦W2, where 2 F is a minimum processing size by photolithography.

### Claim 4 (depends on 1)

The method of claim 1,
wherein the device includes a memory cell array part, a core part adjacent to the memory cell array part, and a peripheral circuit part surrounding the memory cell array part and the core part,
the first sidewall mask is used for patterning of the memory cell array part, and
the second sidewall mask is used for patterning of the core part arranged around the memory cell array part.

### Claim 5 (depends on 1)

The method of claim 1,
wherein the first and second patterns are used as a hard mask.

### Claim 6 (depends on 1)

The method of claim 1,
wherein the first and second patterns are used for patterning of an active area and a conductive line having a line-and-space pattern.

### Claim 7 (depends on 1)

The method of claim 1,
wherein the second pattern is used for patterning of a gate electrode of a FET.

### Claim 8 (depends on 1)

The method of claim 1,
wherein one of the first and second layers is amorphous silicon including impurities and the other is amorphous silicon including no impurity.

### Claim 9 (depends on 1)

The method of claim 1,
wherein the covering material has a stacked structure of three layers or more including the first and second layers and each layer of the stacked structure is one of amorphous silicon including impurities, amorphous silicon including no impurity, and an insulating material.

### Claim 10

A method of manufacturing a semiconductor device, the method comprising:
forming a core having first and second parts on a processed material;
forming a covering material having a stacked layer comprising first and second layers, the covering material covering an upper surface and a side surface of the core;
removing the second layer covering the first part of the core;
forming a first sidewall mask having the first layer on the side surface of the first part of the core and a second sidewall mask having the first and second layers on the side surface of the second part of the core by etching the covering material to expose a surface of the processed material:
removing the core; and
forming a pattern having a first width of W1 and a second width of W2 by etching the processed material in condition of using the first and second sidewall masks.

### Claim 11 (depends on 10)

The method of claim 10,
wherein the width W1 of the first sidewall mask is 1 F and the width W2 of the second sidewall mask is 1 F<W2<2 F, where 2 F is a minimum processing size by photolithography.

### Claim 12 (depends on 10)

The method of claim 10,
wherein the width W1 of the first sidewall mask is 1 F and the width W2 of the second sidewall mask is 2 F≦W2, where 2 F is a minimum processing size by photolithography.

### Claim 13 (depends on 10)

The method of claim 10,
wherein the device includes a memory cell array part, a core part adjacent to the memory cell array part, and a peripheral circuit part surrounding the memory cell array part and the core part,
the first sidewall mask is used for patterning of the memory cell array part, and
the second sidewall mask is used for patterning of the core part arranged around the memory cell array part.

### Claim 14 (depends on 10)

The method of claim 10,
wherein the pattern is used as a hard mask.

### Claim 15 (depends on 10)

The method of claim 10,
wherein the pattern is used for patterning of an active area and a conductive line having a line-and space pattern.

### Claim 16 (depends on 10)

The method of claim 10,
wherein the pattern is used for patterning of a gate electrode of a FET.

### Claim 17 (depends on 10)

The method of claim 10,
wherein one of the first and second layers is amorphous silicon including impurities and the other is amorphous silicon including no impurity.

### Claim 18 (depends on 10)

The method of claim 10,
wherein the covering material has a stacked structure of three layers or more including the first and second layers and each layer of the stacked structure is one of amorphous silicon including impurities, amorphous silicon including no impurity, and an insulating material.