# US 8,785,324 B2 · Interconnect structure for semiconductor devices

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- Number: US 8,785,324 B2
- Document ID: US8785324B2
- Status: Granted
- Kind: B2
- Application number: 13/710,168
- Filed: 2012-12-10
- Published: 2013-04-25
- Granted: 2014-07-22
- Earliest claimed: 2007-03-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hui-Lin Chang; Hung Chun Tsai; Yung-Cheng Lu; Syun-Ming Jang
- Web page: https://patentgrep.com/patent/US8785324B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10P 14/414: {of metal-silicide materials}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/033: {in openings in dielectrics}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/055: {by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/064: {by modifying the conductivity of conductive parts, e.g. by alloying}
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/43: Layouts of interconnections
- H10W 20/4424: {Copper alloys}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a dielectric layer on a substrate;
embedding a conductive material into the dielectric layer, the conductive material comprising a first material and having a recess, wherein the recess has a curved top surface; and
siliciding the conductive material to form an alloy layer at least partially within the recess, the alloy layer comprising the first material and a second material, the second material comprising germanium, arsenic, tungsten, or gallium, wherein the siliciding the conductive material further comprises:
introducing a first precursor material to the conductive material, the first precursor material being a silicon containing precursor material; and
introducing a second precursor material to the conductive material, the second precursor material containing the second material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the siliciding the conductive material further comprises forming a seed layer of silicon on the conductive material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the introducing the first precursor material and the introducing the second precursor material are begun simultaneously.

### Claim 4 (depends on 1)

The method of claim 1, wherein the introducing the first precursor material is begun after the introducing the second precursor material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the conductive material comprises copper.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a barrier layer between the conductive material and the dielectric layer.

### Claim 7

A method of manufacturing a semiconductor device, the method comprising:
embedding a conductor into a dielectric layer, the conductor comprising a first material and having a concave top surface; and
forming a silicide layer on the conductor, the silicide layer comprising the first material and germanium, arsenic, tungsten, or gallium, wherein the forming the silicide layer further comprises:
introducing a first precursor material to the conductor, the first precursor material being a silicon containing precursor material; and
introducing a second precursor material to the conductor, the second precursor material containing the second material.

### Claim 8 (depends on 7)

The method of claim 7, wherein the forming the silicide layer further comprises forming a seed layer of silicon on the conductor.

### Claim 9 (depends on 7)

The method of claim 7, wherein the introducing the first precursor material and the introducing the second precursor material are begun simultaneously.

### Claim 10 (depends on 7)

The method of claim 7, wherein the introducing the first precursor material is begun after the introducing the second precursor material.

### Claim 11 (depends on 7)

The method of claim 7, wherein the conductor comprises copper.

### Claim 12 (depends on 7)

The method of claim 7, further comprising forming a barrier layer between the conductor and the dielectric layer.

### Claim 13

A method of manufacturing a semiconductor device, the method comprising;
forming an opening in a dielectric layer over a substrate;
embedding a first conductive material into the opening, the first conductive material having a curved top surface; and
siliciding the curved top surface to form an alloy, the alloy comprising the first conductive material and germanium, arsenic, tungsten, or gallium, wherein the siliciding the curved top surface further comprises:
introducing a first precursor material to the first conductive material, the first precursor material being a silicon containing precursor material; and
introducing a second precursor material to the first conductive material, the second precursor material containing the second material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the siliciding the curved top surface further comprises forming a seed layer of silicon on the first conductive material.

### Claim 15 (depends on 13)

The method of claim 13, wherein the introducing the first precursor material and the introducing the second precursor material are begun simultaneously.

### Claim 16 (depends on 13)

The method of claim 13, wherein the first conductive material comprises copper.

### Claim 17 (depends on 13)

The method of claim 13, further comprising forming a barrier layer between the first conductive material and the dielectric layer.