# US 8,785,323 B2 · Method of forming an interconnect structure having an enlarged region

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,785,323 B2
- Document ID: US8785323B2
- Status: Granted
- Kind: B2
- Application number: 13/953,418
- Filed: 2013-07-29
- Published: 2013-11-28
- Granted: 2014-07-22
- Earliest claimed: 2004-11-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chien-Jung Wang
- Web page: https://patentgrep.com/patent/US8785323B2

## CPC

- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

## Claims

### Claim 1

A method of forming an interconnect structure, the method comprising:
forming a via through a dielectric layer;
forming a conductive line in the dielectric layer over the via, the conductive line electrically coupling a conductive region to the via; and
forming a redundant line in the dielectric layer, the redundant line being in electrical contact to only the conductive region.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a plurality of redundant lines, each of the redundant lines being in electrical contact to only the conductive region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the redundant line extends from a first side of the conductive region and the conductive line extends from a second side of the conductive region, the first side being a different side than the first side.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first side is adjacent to the second side.

### Claim 5 (depends on 1)

The method of claim 1, wherein a longitudinal axis of the redundant line is substantially perpendicular to a longitudinal axis of the conductive line.

### Claim 6 (depends on 1)

The method of claim 1, wherein a width of the redundant line is about equal to a width of the conductive line.

### Claim 7 (depends on 1)

The method of claim 1, wherein the width of the redundant line and the conductive line is about equal to a minimum feature size.

### Claim 8 (depends on 7)

The method of claim 7, wherein the minimum feature size is about 150 nm to about 250 nm.

### Claim 9 (depends on 1)

The method of claim 1, wherein a length of the redundant line is about equal to or greater than a length of the conductive line.