# US 8,785,322 B2 · Devices and methods to optimize materials and properties for replacement metal gate structures

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- Number: US 8,785,322 B2
- Document ID: US8785322B2
- Status: Granted
- Kind: B2
- Application number: 13/017,809
- Filed: 2011-01-31
- Published: 2012-08-02
- Granted: 2014-07-22
- Earliest claimed: 2011-01-31
- Assignees: International Business Machines Corporation
- Applicants: Takashi Ando; Christian Lavoie; Vijay Narayanan
- Inventors: Takashi Ando; Christian Lavoie; Vijay Narayanan
- Web page: https://patentgrep.com/patent/US8785322B2

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 30/0273: {forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 30/208: {of electrically inactive species}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

## Claims

### Claim 1

A method for device fabrication, comprising:
forming a gate structure with a sacrificial material and raised source/drain regions adjacent to the gate structure;
patterning contact trenches in a dielectric layer over the raised source/drain regions;
forming silicided regions on the raised source/drain regions at bottoms of the contact trenches to localize silicide formation;
processing the silicided regions to build resistance to subsequent thermal processing wherein the processing includes introducing impurities through the contact trenches into the silicided regions of the raised source/drain regions to reduce thermal degradation of the silicided regions;
forming contacts in contact with the silicided regions; and
after forming the silicided regions and the contacts, removing the sacrificial material and replacing the sacrificial material with a replacement conductor.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the impurities include one or more of B, As, P, Se, S and F.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein processing includes forming materials resistant to agglomeration in the silicided regions.

### Claim 4 (depends on 3)

The method as recited in claim 3, wherein the materials resistant to agglomeration include Pt, C, and/or ternary alloys.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein processing includes providing for Schottky barrier adjustment and thermal stability in the silicided regions.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein replacing the sacrificial material with a replacement conductor includes replacing the sacrificial material with a metal.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein replacing the sacrificial material with a replacement conductor includes forming a high dielectric constant dielectric and forming a metal gate conductor in the gate structure.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein the method maintains thermal degradation resistance during one or more annealing processes.

### Claim 9 (depends on 1)

The method as recited in claim 1, wherein forming a gate structure with a sacrificial material includes forming a gate dielectric with a high dielectric constant material.

### Claim 10

A method for device fabrication, comprising:
forming a gate structure with a sacrificial material and raised source/drain regions adjacent to the gate structure;
processing the raised source/drain regions adjacent to the gate structure to build resistance to subsequent thermal processing;
forming contact trenches in a dielectric layer over the raised source/drain regions;
forming silicided regions on the raised source/drain regions in the contact trenches;
processing the silicided regions to build resistance to subsequent thermal processing wherein the processing includes introducing impurities through the contact trenches into the silicided regions of the raised source/drain regions to reduce thermal degradation of the silicided regions;
forming contacts in the contact trenches; and
after forming the silicided regions and the contacts, removing the sacrificial material and replacing the sacrificial material with a replacement conductor.

### Claim 11 (depends on 10)

The method as recited in claim 10, wherein the impurities include one or more of B, As, P, Se, S and F.

### Claim 12 (depends on 10)

The method as recited in claim 10, wherein processing the silicided regions includes forming materials resistant to silicide agglomeration.

### Claim 13 (depends on 12)

The method as recited in claim 12, wherein the materials resistant to silicide agglomeration include Pt, C, and/or ternary alloys.

### Claim 14 (depends on 10)

The method as recited in claim 10, wherein replacing the sacrificial material with a replacement conductor includes replacing the sacrificial material with a metal.

### Claim 15 (depends on 10)

The method as recited in claim 10, wherein replacing the sacrificial material with a replacement conductor includes forming a high dielectric constant dielectric and forming a metal gate conductor in the gate structure.

### Claim 16 (depends on 10)

The method as recited in claim 10, wherein processing source/drain regions includes performing one or more annealing processes.

### Claim 17 (depends on 10)

The method as recited in claim 10, wherein processing the silicided regions includes providing for Schottky barrier adjustment and thermal stability in the silicided regions.

### Claim 18 (depends on 10)

The method as recited in claim 10, wherein forming a gate structure with a sacrificial material includes forming a gate dielectric with a high dielectric constant material.