# US 8,785,321 B2 · Low resistance and reliable copper interconnects by variable doping

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- Number: US 8,785,321 B2
- Document ID: US8785321B2
- Status: Granted
- Kind: B2
- Application number: 13/249,823
- Filed: 2011-09-30
- Published: 2012-01-26
- Granted: 2014-07-22
- Earliest claimed: 2003-08-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Ting-Chu Ko; Ming-Hsing Tsai; Chien-Hsueh Shih
- Inventors: Ting-Chu Ko; Ming-Hsing Tsai; Chien-Hsueh Shih
- Web page: https://patentgrep.com/patent/US8785321B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

## Claims

### Claim 1

A method for fabricating a metal alloy interconnect in a semiconductor device, the method comprising:
defining an interconnect boundary profile, comprising vias or trenches, on a substrate material;
plating a primary metal and one or more impurity metals together to form a first layer of interconnect along the interconnect boundary profile, wherein the first layer of interconnect comprising a primary metal and one or more impurity metals; and
plating a primary metal and one or more impurity metals together to form a second layer of interconnect over the first layer of interconnect, wherein the second layer of interconnect comprising the primary metal with one or more impurity metals, wherein the second layer of interconnect is thicker than the first layer of interconnect and the second layer of interconnect has a lower electrical resistance than the first layer of interconnect.

### Claim 2 (depends on 1)

The method of claim 1, wherein the impurity metals have lower reduction potential than the primary metal.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second layer of interconnect has a lower concentration of impurity metals than the first layer of interconnect.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plating processes include at least one electro-chemical plating process or at least one electroless plating process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the plating processes include adjusting plating temperatures in the processes, thereby adjusting a thermal budget for plating the metal alloy interconnect layers.

### Claim 6 (depends on 1)

The method of claim 1, further comprising depositing a seed layer comprising the primary metal on the substrate before plating the first layer of interconnect, wherein the seed layer is underneath the first layer of interconnect.

### Claim 7 (depends on 6)

The method of claim 6, wherein the primary metal comprises Cu.

### Claim 8 (depends on 6)

The method of claim 6, wherein the seed layer is plated on the substrate.

### Claim 9 (depends on 6)

The method of claim 6, wherein the seed layer is a pure primary metal.

### Claim 10 (depends on 1)

The method of claim 1, wherein the one or more impurity metals is Sn.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first layer of interconnect substantially fills the vias for improved electromigration resistance of the vias.

### Claim 12

A method for fabricating a metal alloy interconnect in a semiconductor device, the method comprising:
defining an interconnect boundary profile, comprising vias or trenches, on a substrate material;
depositing a seed layer comprising a primary metal along the interconnect boundary profile on the substrate material;
plating the primary metal and one or more impurities together to form a first layer of interconnect over the seed layer, wherein the first layer of interconnect comprising the primary metal and one or more impurities; and
plating the primary metal and one or more impurities together to form a second layer of interconnect over the first layer of interconnect, the second layer of interconnect comprising the primary metal and one or more impurities, wherein the second layer of interconnect is thicker than the first layer of interconnect and the second layer of interconnect has a lower electrical resistance than the first layer of interconnect.

### Claim 13 (depends on 12)

The method of claim 12, wherein the impurities have lower reduction potential than the primary metal.

### Claim 14 (depends on 12)

The method of claim 12, wherein the second layer of interconnect has a lower concentration of impurities than the first layer of interconnect.

### Claim 15 (depends on 12)

The method of claim 12, wherein the plating steps include at least one electro-chemical plating process or at least one electroless plating process.

### Claim 16 (depends on 12)

The method of claim 12, wherein the plating processes are further enhanced by adjusting plating temperatures in the processes, thereby adjusting a thermal budget for fabricating the metal alloy interconnect.

### Claim 17 (depends on 12)

The method of claim 12, wherein the primary metal comprises Cu.

### Claim 18 (depends on 17)

The method of claim 17, wherein the seed layer is a pure primary metal.

### Claim 19 (depends on 12)

The method of claim 12, wherein the first layer of interconnect substantially fills the vias for improved electromigration resistance of the vias.

### Claim 20 (depends on 12)

The method of claim 12, wherein the seed layer is plated on the substrate.