# US 8,785,318 B2 · Semiconductor device and a method of manufacturing the same

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- Number: US 8,785,318 B2
- Document ID: US8785318B2
- Status: Granted
- Kind: B2
- Application number: 14/012,937
- Filed: 2013-08-28
- Published: 2013-12-26
- Granted: 2014-07-22
- Earliest claimed: 2007-11-09
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Shinya Suzuki
- Web page: https://patentgrep.com/patent/US8785318B2

## CPC

- G02F 1/1345: Conductors connecting electrodes to cell terminals
- G02F 1/13306: {Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence)}
- G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/13458: {Terminal pads}
- H10D 86/80: characterised by multiple passive components, e.g. resistors, capacitors or inductors
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 95/064: {the removal being chemical etching}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/43: Layouts of interconnections
- H10W 72/90: Bond pads, in general
- G02F 1/133302: {Rigid substrates, e.g. inorganic substrates}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/013: {of die-attach connectors}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/074: {of anisotropic conductive adhesives}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising steps of:
(a) forming a semiconductor element in a semiconductor substrate;
(b) forming a first insulating film over the semiconductor element;
(c) forming a pad over the first insulating film;
(d) forming a second insulating film over the pad and the first insulating film such that the second insulating film covers a top surface of the pad and side surfaces of the pad;
(e) forming a third insulating film over the second insulating film;
(f) polishing the third insulating film by a CMP method;
(g) after the step (f), forming a fourth insulating film over the third insulating film, wherein a material of the fourth insulating film is different from materials of the second and third insulating films;
(h) forming an opening which reaches the pad, by etching the second, third, and fourth insulating films; and
(i) forming a bump electrode over the pad and the fourth insulating film, said bump electrode being electrically connected to the pad.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the semiconductor substrate has a pair of long sides and a pair of short sides in planar view;
wherein, in a first direction extending along the pair of long sides, a width of the bump electrode is smaller than a width of the pad, and
wherein, in a second direction extending along the pair of short sides, a width of the bump electrode is larger than the width of the pad.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed of a silicon oxide film.

### Claim 4 (depends on 3)

The method of manufacturing a semiconductor device according to claim 3, wherein the third insulating film is formed of a silicon oxide film.

### Claim 5 (depends on 4)

The method of manufacturing a semiconductor device according to claim 4, wherein the fourth insulating film is formed of a silicon nitride film.

### Claim 6 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein a first wiring, which is electrically connected to the semiconductor element, is formed at the same wiring layer as the pad and
wherein the first wiring is arranged under the bump electrode in a planar view.

### Claim 7 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the first wiring constitutes a power line or a signal line.

### Claim 8 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7,
wherein a dummy pattern, which is not electrically connected to the semiconductor element, is formed at the same wiring layers as the pad, and
wherein the dummy pattern is arranged under the bump electrode in a planar view.

### Claim 9 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the bump electrode includes a cold film, and
wherein the semiconductor device is an LCD driver for a liquid crystal display.