# US 8,785,317 B2 · Wafer level packaging of semiconductor chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,317 B2 - Document ID: US8785317B2 - Status: Granted - Kind: B2 - Application number: 13/690,838 - Filed: 2012-11-30 - Published: 2013-04-18 - Granted: 2014-07-22 - Earliest claimed: 2007-08-29 - Assignees: ATI Technologies ULC - Applicants: ATI Technologies ULC - Inventors: Neil Mclellan; Adam Zbrzezny - Web page: https://patentgrep.com/patent/US8785317B2 ## CPC - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/0198: {batch processes} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/656: Fan-in layouts - H10W 72/01331: {using blanket deposition} - H10W 72/019: {of bond pads} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/251: {Materials} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/129: {forming a chip-scale package [CSP]} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. ## Claims ### Claim 1 A method of manufacturing semiconductor package from a wafer having at least one integrated circuit (IC) formed on an active surface, said method comprising: a) attaching a stiffener to an inactive surface of said wafer; b) forming substantially rectangular under bump metallization (UBM) pads, each one of said UBM pads in communication with said IC, said UBM pads comprising at least a first UBM pad, and a second UBM pad larger than said first UBM pad, wherein said first UBM pad is formed near a periphery of said semiconductor chip package; c) forming solder bumps extending from each of said UBM pads; and d) separating said wafer into semiconductor packages. ### Claim 2 (depends on 1) The method of claim 1, further comprising forming a compliant layer on said active surface of said wafer prior to said forming said UBM pads. ### Claim 3 (depends on 2) The method of claim 2, wherein said compliant layer comprises a dielectric material. ### Claim 4 (depends on 2) The method of claim 2, further comprising forming conductive rerouting to interconnect each of a plurality of die pads corresponding to each IC, to a corresponding one of a plurality of input-output (I/O) pads on said compliant layer, wherein each of said UBM pads is formed on a corresponding one of said I/O pads. ### Claim 5 (depends on 1) The method of claim 1, further comprising thinning said wafer by grinding, prior to said attaching said stiffener. ### Claim 6 (depends on 1) The method of claim 1, wherein said second UBM pad is formed near a center of said semiconductor chip package. ### Claim 7 (depends on 1) The method of claim 1, wherein said stiffener is made of one of organic and metallic materials. ### Claim 8 (depends on 1) The method of claim 1, wherein said UBM pads comprise: at least a first plurality of said UBM pads of a first size placed near a center of said active side spaced apart at a first pitch, and a second plurality of said UBM pads of a second size smaller than said first size and spaced apart at a second pitch, placed near a periphery of said active side. ### Claim 9 A method of manufacturing semiconductor package from a wafer having at least one integrated circuit (IC) formed on an active surface, said method comprising: a) attaching a stiffener to an inactive surface of said wafer; b) forming a first plurality of UBM pads of a first size placed near a center of said active side spaced apart at a first pitch, and a second plurality of said UBM pads of a second size smaller than said first size and spaced apart at a second pitch, placed near a periphery of said active side; c) forming solder bumps extending from at least some of said UBM pads; and d) separating said wafer into semiconductor packages. ### Claim 10 A method of manufacturing semiconductor package from a wafer having at least one integrated circuit (IC) formed on an active surface, said method comprising: a) attaching a stiffener to an inactive surface of said wafer; b) forming substantially rectangular under bump metallization (UBM) pads, each one of said UBM pads in communication with said IC, said UBM pads comprising at least a first UBM pad, and a second UBM pad larger than said first UBM pad, wherein said second UBM pad is formed near a center of said semiconductor chip package; c) forming solder bumps extending from each of said UBM pads; and d) separating said wafer into semiconductor packages. ### Claim 11 (depends on 10) The method of claim 10, wherein said UBM pads comprise: at least a first plurality of said UBM pads of a first size placed near a center of said active side spaced apart at a first pitch, and a second plurality of said UBM pads of a second size smaller than said first size and spaced apart at a second pitch, placed near a periphery of said active side.