# US 8,785,314 B2 · Etch bias homogenization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,314 B2 - Document ID: US8785314B2 - Status: Granted - Kind: B2 - Application number: 13/463,245 - Filed: 2012-05-03 - Published: 2013-11-07 - Granted: 2014-07-22 - Earliest claimed: 2012-05-03 - Assignees: Micron Technology, Inc. - Applicants: Fabio Pellizzer; Hernan A. Castro; Eddie T. Flores - Inventors: Fabio Pellizzer; Hernan A. Castro; Eddie T. Flores - Web page: https://patentgrep.com/patent/US8785314B2 ## CPC - H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped} - H10B 63/24: {of the Ovonic threshold switching type} - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10P 50/667: {by liquid etching only} - H10W 20/031: {of conductive parts of the interconnections} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned. ## Claims ### Claim 1 A method of forming a memory device, comprising: forming conductive material at respective levels over a substrate; electrically coupling a first portion of the conductive material in an active array area to corresponding circuitry on the substrate via a second portion of the conductive material in an inactive array area during patterning of a particular one of the respective levels of conductive material so that each respective level of conductive material has a homogenized etch bias as that of another particular one of the respective levels of conductive material during patterning thereof; and patterning each respective level of conductive material electrically coupled to corresponding circuitry on the substrate. ### Claim 2 (depends on 1) The method of claim 1, wherein patterning each respective level of conductive material includes patterning the conductive material into word and/or bit lines in the active array area. ### Claim 3 (depends on 1) The method of claim 1, wherein electrically coupling each respective level of conductive material to corresponding circuitry on the substrate includes electrically coupling a first conductive material from which conductive lines of an active memory array will be patterned through conductive material at a glue level G1. ### Claim 4 (depends on 3) The method of claim 3, further comprising forming an interconnection between the conductive material from which conductive lines of an active memory array will be patterned and the conductive material at the glue level G1 in a first socket region adjacent an active memory array area. ### Claim 5 (depends on 4) The method of claim 4, further comprising forming an interconnection between the conductive material at the glue level G1 and a lower metal in an area outside the first socket region and the active memory array area. ### Claim 6 (depends on 4) The method of claim 4, wherein electrically coupling each respective level of conductive material to corresponding circuitry on the substrate includes: electrically coupling a second conductive material from which conductive lines of an active memory array will be patterned to a lower metal level in a second socket region; and electrically coupling a third conductive material from which conductive lines of an active memory array will be patterned to the lower metal level in a third socket region. ### Claim 7 (depends on 3) The method of claim 3, wherein electrically coupling conductive material from which conductive lines of an active memory array will be patterned through conductive material at a glue level G1 includes forming a grid of conductive lines in an area outside the socket region and the active memory array area from the conductive material at a glue level G1, the grid of conductive lines being formed around each of a number of inactive arrays. ### Claim 8 (depends on 3) The method of claim 3, further comprising forming an interconnection between a metal level above conductive materials from which conductive lines of the active memory array are patterned in an area outside the socket region and the active memory array area that does not have inactive arrays formed therein. ### Claim 9 A method of forming a memory device, comprising: forming an active memory array in an active array area using a plurality of conductive material levels; forming a number of conductive line socket regions adjacent edges of the array area; forming a number of first inactive arrays in corner regions adjacent a number of conductive line socket regions; and forming a number of second inactive arrays outside of the array area, the number of conductive line socket regions, and the corner regions wherein forming an active memory array in an array area using a plurality of conductive material levels includes: forming conductive material at respective levels over a substrate; electrically coupling a first portion of the conductive material in the active array area to corresponding circuitry on the substrate via a second portion of the conductive material inside the second inactive array area during patterning of a particular one of the respective levels of conductive material so that each respective level of conductive material has a homogenized etch bias as that of another particular one of the respective levels of conductive material during patterning thereof; and patterning each respective level of conductive material electrically coupled to corresponding circuitry on the substrate. ### Claim 10 (depends on 9) The method of claim 9, further comprising forming a grid of conductive lines around each of the second inactive arrays at a first conductive material level lower than the active memory array, wherein the grid of conductive lines is electrically coupled to a conductive material level at a higher elevation in one of the number of conductive line socket regions, and the grid of conductive lines is electrically coupled to a conductive material level at a lower elevation in an area outside the array area and the number of conductive line socket regions. ### Claim 11 (depends on 10) The method of claim 10, wherein forming the grid of conductive lines includes forming an interconnection between first conductive material level lower than the active memory array and a next lower metal level before patterning the grid of conductive lines from the first conductive material level lower than the active memory array. ### Claim 12 (depends on 11) The method of claim 11, wherein forming the grid of conductive lines includes forming the first conductive material over metal levels M1, M2 and M3, the first conductive material being a metal material. ### Claim 13 (depends on 10) The method of claim 10, further comprising forming, inside the grid of conductive lines, local signal paths using the first conductive material level lower than the active memory array, wherein the local signal paths do not intersect the grid of conductive lines around each of the second inactive arrays. ### Claim 14 (depends on 10) The method of claim 10, wherein forming the number of second inactive arrays includes spacing apart the second inactive arrays by less than approximately one micrometer, conductive lines comprising the grid of conductive lines being located in spaces between the second inactive arrays. ### Claim 15 (depends on 10) The method of claim 10, further comprising sizing and placing the second inactive arrays to fill-up available space in an area adjacent the array area and conductive line socket regions over which circuitry associated with the active memory array is formed on a substrate. ### Claim 16 (depends on 9) The method of claim 9, wherein forming the number of second inactive arrays includes forming a number of second inactive arrays having different sizes in areas above circuits formed on a substrate associated with the active memory array. ### Claim 17 A method of forming a memory device, comprising: forming over a substrate a plurality of metal levels metal levels coupled to CMOS devices associated with an active memory array in each of an active array area, an inactive array area, a first socket region, a second socket region, a third socket region, a decoder area, a first peripheral area, and a second peripheral area; electrically coupling the plurality of metal levels metal levels so as to have a homogenized etch bias during patterning thereof by: interconnecting a lowest metal level of the plurality of metal levels to the substrate during patterning of the lowest metal level; interconnecting each higher metal level of the plurality of metal levels to a respective lower metal level of the plurality of metal levels during patterning of each higher metal level; forming a glue metal level over a highest metal level of the plurality of metal levels; interconnecting the glue metal level in the inactive array area to the highest metal level before patterning the glue metal level; forming the active memory array in the array area over the glue metal level; and forming a metal level over the glue level in each of an array area, a first socket region, a second socket region, a third socket region, a decoder area, a first peripheral area, and a second peripheral area. ### Claim 18 (depends on 17) The method of claim 17, wherein interconnecting the glue metal level to the highest metal level of the plurality of metal levels includes interconnecting the glue metal level to the highest metal level only in the decoder area located outside the array area, the first socket region, the second socket region, the third socket region, and the first and second peripheral areas. ### Claim 19 (depends on 18) The method of claim 18, further comprising: interconnecting first conductive lines of the active memory array to the highest metal level of the plurality of metal levels only in the first socket region during patterning of the first conductive lines; and interconnecting second conductive lines of the active memory array to the highest metal level of the plurality of metal levels only in the second socket region during patterning of the second conductive lines. ### Claim 20 (depends on 19) The method of claim 19, further comprising interconnecting the glue metal level to third conductive lines of the active memory array only in the third socket region during patterning of the third conductive lines. ### Claim 21 (depends on 17) The method of claim 17, further comprising interconnecting the M4 metal level to the highest metal level of the plurality of metal levels only in the first peripheral area during patterning of the M4 metal level. ### Claim 22 (depends on 17) The method of claim 17, further comprising; forming a number of inactive arrays in the decoder area over the glue metal level and over the CMOS devices associated with an active memory array; and forming a grid of conductive lines around each of the inactive arrays patterned in the glue metal level. ### Claim 23 (depends on 17) The method of claim 17, further comprising forming a number of inactive arrays in the second peripheral area over the glue metal level and over the CMOS devices associated with an active memory array. ### Claim 24 A method of forming a memory device, comprising: forming conductive material at respective levels over a substrate; electrically coupling each respective level of conductive material to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof; and patterning each respective level of conductive material electrically coupled to corresponding circuitry on the substrate, wherein electrically coupling conductive material from which conductive lines of an active memory array will be patterned through conductive material at a glue level G1 includes forming a grid of conductive lines in an area outside the socket region and an area of the active memory array from the conductive material at a glue level G1, the grid of conductive lines being formed around each of a number of inactive arrays. ### Claim 25 (depends on 24) The method of claim 24, wherein electrically coupling each respective level of conductive material to corresponding circuitry on the substrate includes electrically coupling a first conductive material from which conductive lines of an active memory array will be patterned through conductive material at a glue level G1. ### Claim 26 (depends on 25) The method of claim 25, further comprising forming an interconnection between the conductive material at a glue level G1 and a lower metal in an area outside a first socket region and an active memory array area. ### Claim 27 (depends on 25) The method of claim 25, wherein electrically coupling each respective level of conductive material to corresponding circuitry on the substrate includes: electrically coupling a second conductive material from which conductive lines of an active memory array will be patterned to a lower metal level in a second socket region; and electrically coupling a third conductive material from which conductive lines of an active memory array will be patterned to the lower metal level in a third socket region. ### Claim 28 (depends on 25) The method of claim 25, further comprising forming an interconnection between a metal level above conductive materials from which conductive lines of an active memory array are patterned in an area outside the socket region and an active memory array area that does not have inactive arrays formed therein. ### Claim 29 (depends on 24) The method of claim 24, further comprising forming an interconnection between the conductive material at a glue level G1 and a lower metal in an area outside a first socket region and an active memory array area. ### Claim 30 (depends on 24) The method of claim 24, wherein electrically coupling each respective level of conductive material to corresponding circuitry on the substrate includes: electrically coupling a second conductive material from which conductive lines of an active memory array will be patterned to a lower metal level in a second socket region; and electrically coupling a third conductive material from which conductive lines of an active memory array will be patterned to the lower metal level in a third socket region. ### Claim 31 (depends on 24) The method of claim 24, further comprising forming an interconnection between a metal level above conductive materials from which conductive lines of an active memory array are patterned in an area outside the socket region and an area of the active memory array that does not have inactive arrays formed therein.