# US 8,785,312 B2 · Conductive layers for hafnium silicon oxynitride > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,312 B2 - Document ID: US8785312B2 - Status: Granted - Kind: B2 - Application number: 13/305,338 - Filed: 2011-11-28 - Published: 2012-03-22 - Granted: 2014-07-22 - Earliest claimed: 2006-02-16 - Assignees: Micron Technology, Inc. - Applicants: Kie Y. Ahn; Leonard Forbes - Inventors: Kie Y. Ahn; Leonard Forbes - Web page: https://patentgrep.com/patent/US8785312B2 ## CPC - H10D 64/683: {being parallel to the channel plane} - C23C 16/30: Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides - C23C 16/45529: {specially adapted for making a layer stack of alternating different compositions or gradient compositions} - C23C 16/45531: {specially adapted for making ternary or higher compositions} - H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)} - H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)} - H10D 64/68: characterised by the insulator, e.g. by the gate insulator - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10P 14/693: {the material containing hafnium, e.g. HfSiOx or HfSiON} - H10D 1/68: Capacitors having no potential barriers - H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD} - H10P 14/69397: {the material containing two or more metal elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. ## Claims ### Claim 1 A method comprising: forming a dielectric including hafnium silicon oxynitride, the hafnium silicon oxynitride being HfxSiyOzNr with x>0, y>0, z>0, and r>0; forming the hafnium silicon oxynitride doped with one or more elements other than hafnium or silicon, such that the hafnium silicon oxynitride is maintained as a hafnium silicon oxynitride structure, by using a monolayer or partial monolayer sequencing process and by substituting a sequence of the one or more elements for a hafnium sequence of a plurality of hafnium sequences or substituting a sequence of the one or more elements for a silicon sequence of a plurality of silicon sequences in the monolayer or partial monolayer sequencing process such that the one or more elements are included in a completed structure of the hafnium silicon oxynitride; and forming a conductive material coupled to the dielectric. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the conductive includes forming titanium nitride coupled to the hafnium silicon oxynitride. ### Claim 3 (depends on 1) The method of claim 1, wherein forming the conductive includes forming tantalum coupled to the hafnium silicon oxynitride. ### Claim 4 (depends on 1) The method of claim 1, wherein forming the dielectric includes forming the dielectric as a nanolaminate. ### Claim 5 (depends on 1) The method of claim 1, wherein forming the conductive material includes forming the conductive material using the monolayer or partial monolayer sequencing process. ### Claim 6 (depends on 5) The method of claim 5, wherein using the monolayer or partial monolayer sequencing process includes using atomic layer deposition. ### Claim 7 (depends on 1) The method of claim 1, wherein forming hafnium silicon oxynitride includes: forming alternating layers of hafnium oxide and silicon nitride; and annealing the alternating layers of hafnium oxide and silicon nitride to form hafnium silicon oxynitride. ### Claim 8 (depends on 7) The method of claim 7, wherein annealing includes annealing in a nitrogen ambient. ### Claim 9 (depends on 1) The method of claim 1, wherein the method includes: forming tantalum as the conductive material coupled to the hafnium silicon oxynitride such that the tantalum is formed as a gate with the hafnium silicon oxynitride as a gate insulator in a PMOS transistor of a CMOS structure; and forming a titanium nitride as a gate on another region of hafnium silicon oxynitride in a NMOS transistor of the CMOS structure. ### Claim 10 (depends on 1) The method of claim 1, wherein forming the dielectric includes forming the dielectric essentially as the hafnium silicon oxynitride. ### Claim 11 (depends on 1) The method of claim 1, wherein forming the dielectric includes forming a stack of dielectrics. ### Claim 12 (depends on 11) The method of claim 11, wherein forming the stack of dielectrics includes forming an insulating metal oxide. ### Claim 13 A method comprising: forming a memory having a dielectric including hafnium silicon oxynitride, the hafnium silicon oxynitride being HfxSiyOzNr with x>0, y>0, z>0, and r>0; forming the hafnium silicon oxynitride doped with one or more elements other than hafnium or silicon, such that the hafnium silicon oxynitride is maintained as a hafnium silicon oxynitride structure, by using a monolayer or partial monolayer sequencing process and substituting a sequence of the one or more elements for a hafnium sequence of a plurality of hafnium sequences or substituting a sequence of the one or more elements for a silicon sequence of a plurality of silicon sequences in the monolayer or partial monolayer sequencing process such that the one or more elements are included in a completed structure of the hafnium silicon oxynitride; and forming one or more of a titanium nitride or tantalum coupled to the dielectric. ### Claim 14 (depends on 13) The method of claim 13, wherein the method includes forming the dielectric as a nanolaminate containing silicon oxide as a charge storage region of the nanolaminate. ### Claim 15 (depends on 13) The method of claim 13, wherein the method includes forming titanium nitride as a gate with the hafnium silicon oxynitride as a gate insulator in a NMOS transistor and forming tantalum as a gate with a region of hafnium silicon oxynitride as a gate insulator in a PMOS transistor such that the NMOS transistor and the PMOS transistor have substantially symmetrical threshold voltages. ### Claim 16 (depends on 1) The method of claim 1, wherein hafnium silicon oxynitride is formed in each cycle of the monolayer or partial monolayer sequencing process. ### Claim 17 (depends on 1) The method of claim 1, wherein a number of hafnium sequence and a number of silicon sequences are conducted in each cycle of the monolayer or partial monolayer sequencing process such that the hafnium silicon oxynitride is formed being a hafnium-rich hafnium silicon oxynitride.