# US 8,785,291 B2 · Post-gate shallow trench isolation structure formation

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- Number: US 8,785,291 B2
- Document ID: US8785291B2
- Status: Granted
- Kind: B2
- Application number: 13/277,259
- Filed: 2011-10-20
- Published: 2013-04-25
- Granted: 2014-07-22
- Earliest claimed: 2011-10-20
- Assignees: International Business Machines Corporation
- Applicants: Xiaojun Yu; Brian J. Greene; Yue Liang
- Inventors: Xiaojun Yu; Brian J. Greene; Yue Liang
- Web page: https://patentgrep.com/patent/US8785291B2

## CPC

- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/071: {of dielectric parts thereof}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming a gate stack including a gate dielectric and a gate electrode on a semiconductor substrate;
removing end portions of said gate electrode by an anisotropic etch, wherein two sidewalls of said gate electrode that become physically exposed during said anisotropic etch are vertically coincident with sidewalls of one of at least one semiconductor portion;
forming, after removing said end portions of said gate electrode, a trench laterally surrounding a contiguous set of said at least one semiconductor portion in said semiconductor substrate after forming said gate stack; and
filling said trench with a dielectric material, wherein a shallow trench isolation structure comprising at least a dielectric material portion embedded in said semiconductor substrate and laterally surrounding said contiguous set of said at least one semiconductor portion is formed.

### Claim 2 (depends on 1)

The method of claim 1, further comprising patterning said gate stack and a semiconductor layer including said contiguous set of said at least one semiconductor portion by an anisotropic etch.

### Claim 3 (depends on 1)

The method claim 1, further comprising forming a gate spacer on sidewalls of said gate electrode.

### Claim 4 (depends on 1)

The method of claim 1, wherein said contiguous set of said at least one semiconductor portion includes a single crystalline semiconductor portion underlying said gate electrode and having a first lattice constant, an embedded single crystalline source region laterally contacting said single crystalline semiconductor portion and having a second lattice constant different from said first lattice constant, and an embedded drain region laterally contacting said single crystalline semiconductor portion and having said second lattice constant.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a planarized material layer over said gate electrode and said semiconductor substrate;
patterning said planarized material layer to form a planarized material portion; and
transferring a pattern in said planarized material portion into said gate electrode and an upper portion of said semiconductor substrate during said forming of said trenches.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
applying a photoresist over said gate stack and said semiconductor substrate;
forming a trench laterally surrounding a contiguous set of at least one semiconductor portion in said semiconductor substrate after forming said gate stack by transferring a pattern in said photoresist into said gate stack and said semiconductor substrate employing an anisotropic etch, wherein said trench is formed during said anisotropic etch; and
depositing said dielectric material in said trench employing a deposition process that does not deposit said dielectric material over said gate electrode.

### Claim 7 (depends on 2)

The method of claim 2, wherein one of said two physically exposed sidewalls of said gate electrode is vertically coincident with a sidewall of one of said at least one semiconductor portion after said anisotropic etch.

### Claim 8 (depends on 3)

The method of claim 3, wherein said gate spacer becomes divided during said anisotropic etch into a source-side gate spacer located on one side of a remaining portion of said gate electrode and a drain-side gate spacer located on an opposite side of said remaining portion of said gate electrode, and said source-side gate spacer is not contiguous with said drain-side gate spacer.

### Claim 9 (depends on 4)

The method of claim 4, wherein each of said embedded source region and said embedded drain region has a top surface that contacts sidewalls of said shallow trench isolation structure at right angle throughout an entirety of a periphery of said top surface that is in contact with said shallow trench isolation structure.

### Claim 10 (depends on 5)

The method of claim 5, further comprising:
forming a shallow trench dielectric layer filling said trench and overlying said planarized material portion by depositing said dielectric material; and
recessing said shallow trench dielectric layer below a top planar surface of said planarized material layer, wherein a remaining portion of said shallow trench dielectric layer is said shallow trench isolation structure.

### Claim 11 (depends on 5)

The method of claim 5, further comprising:
forming a shallow trench dielectric layer filling said trench and overlying said planarized material portion by depositing said dielectric material; and
planarizing said shallow trench dielectric layer to form said shallow trench isolation structure, wherein a top surface of said shallow trench isolation structure is coplanar with a top surface of said planarized material layer after said planarization.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
removing said planarized material layer selective to said shallow trench isolation structure; and
forming a contact-level dielectric layer over said gate electrode and said shallow trench isolation structure.

### Claim 13

A method of forming a semiconductor structure comprising:
forming a gate stack including a gate dielectric and a gate electrode on a semiconductor substrate;
forming a planarized material layer over said gate electrode and said semiconductor substrate;
patterning said planarized material layer to form a planarized material portion;
forming a trench laterally surrounding a contiguous set of at least one semiconductor portion in said semiconductor substrate after forming said gate stack;
transferring a pattern in said planarized material portion into said gate electrode and an upper portion of said semiconductor substrate during said forming of said trenches; and
filling said trench with a dielectric material, wherein a shallow trench isolation structure comprising at least a dielectric material portion embedded in said semiconductor substrate and laterally surrounding said contiguous set of said at least one semiconductor portion is formed.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a shallow trench dielectric layer filling said trench and overlying said planarized material portion by depositing said dielectric material; and
recessing said shallow trench dielectric layer below a top planar surface of said planarized material layer, wherein a remaining portion of said shallow trench dielectric layer is said shallow trench isolation structure.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
forming a shallow trench dielectric layer filling said trench and overlying said planarized material portion by depositing said dielectric material; and
planarizing said shallow trench dielectric layer to form said shallow trench isolation structure, wherein a top surface of said shallow trench isolation structure is coplanar with a top surface of said planarized material layer after said planarization.

### Claim 16 (depends on 13)

The method of claim 13, further comprising removing, prior to forming said trench, end portions of said gate electrode by an anisotropic etch, wherein two sidewalls of said gate electrode that become physically exposed during said anisotropic etch are vertically coincident with sidewalls of one of said at least one semiconductor portion.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
removing said planarized material layer selective to said shallow trench isolation structure; and
forming a contact-level dielectric layer over said gate electrode and said shallow trench isolation structure.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
applying a photoresist over said gate stack and said semiconductor substrate; and
transferring a pattern in said photoresist into said gate stack and said semiconductor substrate employing an anisotropic etch, wherein said trench is formed during said anisotropic etch.

### Claim 19

A method of forming a semiconductor structure comprising:
forming a gate stack including a gate dielectric and a gate electrode on a semiconductor substrate;
applying a photoresist over said gate stack and said semiconductor substrate;
forming a trench laterally surrounding a contiguous set of at least one semiconductor portion in said semiconductor substrate after forming said gate stack by transferring a pattern in said photoresist into said gate stack and said semiconductor substrate employing an anisotropic etch, wherein said trench is formed during said anisotropic etch; and
filling said trench with a dielectric material, wherein a shallow trench isolation structure comprising at least a dielectric material portion embedded in said semiconductor substrate and laterally surrounding said contiguous set of said at least one semiconductor portion is formed.

### Claim 20 (depends on 19)

The method of claim 19, further comprising depositing said dielectric material in said trench employing a deposition process that does not deposit said dielectric material over said gate electrode.