# US 8,785,289 B2 · Integrated decoupling capacitor employing conductive through-substrate vias

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- Number: US 8,785,289 B2
- Document ID: US8785289B2
- Status: Granted
- Kind: B2
- Application number: 13/975,519
- Filed: 2013-08-26
- Published: 2013-12-26
- Granted: 2014-07-22
- Earliest claimed: 2009-11-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Tae Hong Kim; Michael F. McAllister; Michael J. Shapiro; Edmund J. Sprogis
- Web page: https://patentgrep.com/patent/US8785289B2

## CPC

- H10D 1/68: Capacitors having no potential barriers
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 90/00: Package configurations
- H10W 70/635: {Through-vias}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming a capacitor and an laterally-insulated conductive through-substrate connection structure in a semiconductor substrate,
wherein said forming said laterally-insulated conductive through-substrate connection structure and said capacitor comprises:
forming a dielectric tubular structure around a first through-substrate cavity formed in said semiconductor substrate;
filling said first through-substrate cavity with a disposable material;
forming an outer electrode by doping a portion of said semiconductor substrate around a second through-substrate cavity;
forming a node dielectric on a surface of said second through-substrate cavity; removing said disposable material from said first through-substrate cavity within said dielectric tubular structure; filling said first through-substrate cavity with said dielectric tubular structure with a conductive material; and
forming an inner electrode by filling said second through-substrate cavity with said conductive material.

### Claim 2 (depends on 1)

The method of claim 1, wherein said inner electrode constitutes a first conductive through-substrate via (TSV) structure, a second conductive TSV structure is formed in said cavity filled by said conductive material, and said first conductive TSV structure and said second conductive TSV structure are formed concurrently.

### Claim 3 (depends on 2)

The method of claim 2, wherein at least one of the first TSV, and the second TSV is composed of a material selected from the group consisting of doped polysilicon, doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.

### Claim 4 (depends on 2)

The method of claim 2, wherein at least one of the first TSV and the second TSV by electroplating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.

### Claim 5 (depends on 1)

The method of claim 1, wherein the disposable material is polysilicon or amorphous silicon.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming said node dielectric directly on sidewalls of said doped tubular portion while said disposable material is present in said semiconductor substrate.

### Claim 7 (depends on 6)

The method of claim 6, wherein the node dielectric has a thickness ranging from 3 nm to 30 nm.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
filling said second through-substrate cavity with a second disposable material after forming said outer electrode;
forming a hard mask layer on one side of said semiconductor substrate; and
removing said disposable material and said second disposable material employing said hard mask layer as an etch mask.

### Claim 9

A method of forming a semiconductor structure comprising:
providing a semiconductor chip including:
providing a semiconductor substrate;
forming at least one capacitor embedded in said semiconductor substrate, said at least one capacitor including an inner electrode comprising a conductive through-substrate via (TSV) structure; and
forming at least one laterally-insulated conductive through-substrate connection structure, wherein said forming at least one laterally-insulated conductive through-substrate connection structure comprises:
forming a dielectric tubular structure around a first through-substrate cavity formed in said semiconductor substrate,
filling said first through-substrate cavity with a disposable material,
removing said disposable material from said first through-substrate cavity within said dielectric tubular structure before forming said inner electrode of said at least one capacitor, and
filling said cavity within said dielectric tubular structure with a conductive material; and
electrically connecting said semiconductor chip to a mounting structure employing an array of solder balls.

### Claim 10 (depends on 9)

The method of claim 9, wherein the conductive TSV is composed of a material selected from the group consisting of doped polysilicon, doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.

### Claim 11 (depends on 9)

The method of claim 9, wherein the mounting structure includes an interposer structure.

### Claim 12 (depends on 9)

The method of claim 9, wherein the semiconductor chip further comprises field effect transistors, thyristors, bipolar transistors, diodes and combinations thereof.

### Claim 13 (depends on 9)

The method of claim 9, wherein the capacitors are decoupling capacitors.

### Claim 14 (depends on 13)

The method of claim 13, wherein the decoupling capacitors have a capacitance ranging from 1 pF to 10 nF.

### Claim 15 (depends on 11)

The method of claim 11, wherein the interposer includes a dielectric layer and a plurality of metal lines.

### Claim 16 (depends on 9)

The method of claim 9, wherein first solder balls among said array are electrically connected to said inner electrodes and first conductive structures on said mounting structure, and second solder balls among said array are electrically connected to conductive TSV structures within said at least one laterally-insulated conductive through-substrate connection structure and second conductive structures on said mounting structure.

### Claim 17 (depends on 9)

The method of claim 9, wherein said mounting structure is selected from a packaging substrate, an interposer structure, and another semiconductor chip.

### Claim 18 (depends on 9)

The method of claim 9, wherein each of said at least one capacitor includes a node dielectric laterally contacting and laterally enclosing said inner electrode and an outer electrode laterally contacting and laterally enclosing a portion of said node dielectric, and each of said at least one laterally-insulated conductive through-substrate connection structure includes a conductive TSV structure and a dielectric tubular structure.