# US 8,785,287 B2 · Method to tune narrow width effect with raised S/D structure

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- Number: US 8,785,287 B2
- Document ID: US8785287B2
- Status: Granted
- Kind: B2
- Application number: 12/803,754
- Filed: 2010-07-06
- Published: 2012-01-12
- Granted: 2014-07-22
- Earliest claimed: 2010-07-06
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: Chunshan Yin; Guangyu Huang; Elgin Quek; Jae Gon Lee; Kian Ming Tan
- Inventors: Chunshan Yin; Guangyu Huang; Elgin Quek; Jae Gon Lee; Kian Ming Tan
- Web page: https://patentgrep.com/patent/US8785287B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
providing a substrate of a first conductivity type;
forming thereon a field effect transistor (FET) structure including a gate, said gate having a gate width, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type;
forming a halo region by implanting dopants of the first conductivity type within the substrate, wherein forming the halo region further comprises, implanting first dopants of the first conductivity type at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width to form a first portion of the halo region and implanting second dopants of the first conductivity type at a second predetermined tilt angle and at a second predetermined twist angle to form a second portion of the halo region, such that a doping concentration at a given depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the given depth below the channel surface near an edge of the first raised S/D region.

### Claim 2 (depends on 1)

The method in accordance with claim 1 wherein the second predetermined twist angle is between about 20 and 70 degrees.

### Claim 3 (depends on 2)

The method in accordance with claim 2 wherein the second predetermined twist angle is about 45 degrees.

### Claim 4 (depends on 1)

The method in accordance with claim 1 wherein the first predetermined tilt angle is equal to the second predetermined tilt angle.

### Claim 5 (depends on 4)

The method in accordance with claim 4 wherein the second predetermined twist angle is between about 20 and 70 degrees.

### Claim 6

A method for forming a field-effect transistor (FET) for increasing a gate threshold of the field effect transistor, the method comprising:
providing a substrate of a first conductivity type;
forming thereon a FET structure including a gate, said gate having a gate width, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type;
implanting at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width dopants of the first conductivity type within the substrate to form an intermediate halo region;
implanting at a second predetermined tilt angle and at a second predetermined twist angle of between about 20 and 70 degrees dopants of the first conductivity type to form a final halo region including the intermediate halo region.

### Claim 7 (depends on 6)

The method in accordance with claim 6 wherein a doping concentration at a predetermined depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the predetermined depth near an edge of the first raised S/D region.

### Claim 8 (depends on 6)

The method in accordance with claim 6 wherein the second predetermined twist angle is about 45 degrees.

### Claim 9 (depends on 6)

The method in accordance with claim 6 wherein the first predetermined tilt angle is equal to the second predetermined tilt angle.

### Claim 10 (depends on 6)

The method in accordance with claim 6 wherein the raised S/D regions are at least partially surrounded by a shallow trench isolation structure.