Semiconductor devices and methods of manufacture thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJi-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
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Abstract
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a channel region in a workpiece;
- and
- forming a source or drain region proximate the channel region comprising:
- recessing the workpiece proximate the channel region using an etch process;
- forming a first conformal liner having a first material composition on a bottom surface of the recess;
- forming a second conformal liner having a second material composition on sidewalls of the recess, the second material composition being different than the first material composition;
- and
- forming a contact resistance-lowering material layer and a channel-stressing material layer in the recess, wherein the contact resistance-lowering material layer comprises SiP, SiAs, or a silicide, and wherein the channel-stressing material layer comprises SiCP or SiCAs.
A method of manufacturing a semiconductor device, the method comprising:
- providing a workpiece;
- forming a channel region in the workpiece;
- forming a gate dielectric over the channel region;
- forming a gate over the gate dielectric;
- and
- forming a source region and a drain region proximate the channel region comprises:
- epitaxially growing a contact resistance-lowering material layer comprising SiP or SiAs, the contact resistance-lowering material layer having a substantially uniform thickness;
- and
- epitaxially growing a channel-stressing material layer comprising SiCP or SiCAs on the contact resistance-lowering material layer.
A semiconductor device, comprising:
- a transistor including:
- a channel region disposed in a workpiece;
- a gate dielectric disposed over the channel region;
- a gate disposed over the gate dielectric;
- and
- a source region and a drain region proximate the channel region, the source region and the drain region being disposed in recesses, the source region and the drain region including:
- a first conformal liner having a first material composition on bottom surfaces of the recesses;
- a second conformal liner having a second material composition on sidewalls of the recesses, the second material composition being different than the first material composition;
- a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide;
- and
- a channel-stressing material layer comprising SiCP or SiCAs.
Dependencies are inferred from the claim text.