# US 8,785,283 B2 · Method for forming semiconductor structure having metal connection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,283 B2 - Document ID: US8785283B2 - Status: Granted - Kind: B2 - Application number: 13/705,183 - Filed: 2012-12-05 - Published: 2014-06-05 - Granted: 2014-07-22 - Earliest claimed: 2012-12-05 - Assignees: United Microelectronics Corp. - Applicants: United Microelectronics Corp. - Inventors: Chieh-Te Chen; Feng-Yi Chang; Chih-Sen Huang; Ching-Wen Hung; Ching-Pin Hsu - Web page: https://patentgrep.com/patent/US8785283B2 ## CPC - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect. ## Claims ### Claim 1 A method for forming a semiconductor structure having at least a metal connect, comprising: providing a substrate; forming a transistor on the substrate and a first inter-dielectric (ILD) layer on the transistor, wherein the transistor comprises a gate and a source/drain region; forming a contact plug in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate, and the top surface of the gate is level with a bottom surface of the first ILD layer; forming a second ILD layer on the first ILD layer and forming a third ILD layer on the second ILD layer, wherein etching rates of the first ILD layer and the second ILD layer are different from each other by using a same etchant; forming a first opening correspondingly above the gate and a second opening correspondingly above the first contact plug in the third ILD layer, wherein a depth of the first opening is greater than that of the second opening; deepening the first opening and the second opening such that the gate is exposed by the first opening and the first contact plug is exposed by the second opening, wherein the bottom of the first opening and the bottom of the second opening are in different layers before the deepening process; and filling a metal layer in the first opening and the second opening to form a first metal connect and a second metal connect respectively. ### Claim 2 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, comprising a first lithography and etching process to form the first opening and a second lithography and etching process to form the second opening. ### Claim 3 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein before the deepening process, the bottom of the first opening is in the first ILD layer and the bottom of the second opening is in the second ILD layer. ### Claim 4 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein before the deepening process, the bottom of the first opening is in the second ILD layer and the bottom of the second opening is in the third ILD layer. ### Claim 5 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein the first ILD layer has an etching selectively with respect to the second ILD layer. ### Claim 6 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein the second ILD layer has an etching selectively with respect to the third ILD layer. ### Claim 7 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein forming the first opening and then forming the second opening. ### Claim 8 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein forming the second opening and then forming the first opening. ### Claim 9 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein the step of forming the first opening and the second opening comprises using a mask layer and a photoresist layer. ### Claim 10 (depends on 9) The method for forming the semiconductor structure having at least a metal connect as in claim 9, wherein the mask layer and the photoresist layer has a tri-layered structure. ### Claim 11 (depends on 10) The method for forming the semiconductor structure having at least a metal connect as in claim 10, wherein the tri-layered structure includes photoresist/SHB layer/ODL layer. ### Claim 12 (depends on 9) The method for forming the semiconductor structure having at least a metal connect as in claim 9, wherein the mask layer includes silicon-containing organic material. ### Claim 13 (depends on 9) The method for forming the semiconductor structure having at least a metal connect as in claim 9, wherein the mask layer includes SiN, SiON or SiC. ### Claim 14 (depends on 1) The method for forming the semiconductor structure having at least a metal connect as in claim 1, wherein the step of forming the first contact plug comprises a planarization process and after the planarization process, a first ILD layer having a predetermined thickness is disposed on the top surface of the gate. ### Claim 15 (depends on 14) The method for forming the semiconductor structure having at least a metal connect as in claim 14, wherein the predetermined thickness is greater than 100 angstroms.