# US 8,785,281 B2 · CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

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- Number: US 8,785,281 B2
- Document ID: US8785281B2
- Status: Granted
- Kind: B2
- Application number: 13/369,707
- Filed: 2012-02-09
- Published: 2012-06-07
- Granted: 2014-07-22
- Earliest claimed: 2006-05-31
- Assignees: International Business Machines Corporation
- Applicants: Tze-Chiang Chen; Meikei Ieong; Rajarao Jammy; Mukesh V. Khare; Chun-yung Sung; Richard Wise; Hongwen Yan; Ying Zhang
- Inventors: Tze-Chiang Chen; Meikei Ieong; Rajarao Jammy; Mukesh V. Khare; Chun-yung Sung; Richard Wise; Hongwen Yan; Ying Zhang
- Web page: https://patentgrep.com/patent/US8785281B2

## CPC

- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

## Claims

### Claim 1

A method for fabricating a semiconductor structure comprising:
forming a first gate stack upon a first region of a semiconductor substrate, said first gate stack comprising a first gate dielectric and a first silicon gate material layer;
forming a material stack of a dielectric material layer and a metal gate material layer, said dielectric material layer including a second gate dielectric and an etch stop layer that comprise a same material or a related material that is deposited or thermally grown, wherein said second gate dielectric is formed upon a second region of said semiconductor substrate that is laterally adjacent to said first region, and said etch stop layer is formed on sidewalls and a top surface of said first gate stack;
forming a block mask over said second gate dielectric;
removing portions of said metal gate material layer and said etch stop layer from above a top surface of said first silicon gate material layer while said block mask protects another portion of said metal gate material layer overlying said second gate dielectric, wherein topmost surfaces of remaining portions of said metal gate material layer and said second gate dielectric are formed above a first horizontal plane including a bottom surface of said first gate stack and below a second horizontal plane including a top surface of said first gate stack, and a remaining portion of said second gate dielectric is in physical contact with said first gate stack;
forming a second silicon gate material layer upon said first gate stack and upon said second gate dielectric after said removal of said portions of said metal gate material layer and said etch stop layer;
forming a planarizing layer upon said silicon gate material layer; and
etching non-selectively said planarizing layer and said second silicon gate material layer, while a vertical portion of said material stack that includes a vertical portion of said metal gate material layer is present on a sidewall surface of a remaining portion of said first silicon gate material layer, to form a second gate stack laterally adjacent said first gate stack.

### Claim 2 (depends on 1)

The method of claim 1, further comprising patterning said first gate stack and said second gate stack to form a first gate over said first region of said semiconductor substrate and a second gate over said second region of said semiconductor substrate, respectively.

### Claim 3 (depends on 1)

The method of claim 1, wherein said first region comprises a first orientation surface semiconductor layer having a first crystallographic orientation, and said second region comprises a second orientation surface semiconductor layer having a second crystallographic orientation different from said first crystallographic orientation.

### Claim 4 (depends on 1)

The method of claim 1, wherein said etching non-selectively uses a plasma etch method.

### Claim 5 (depends on 1)

The method of claim 1, wherein:
said planarizing layer comprises an organic polymer material;
said second silicon gate material layer comprises at least a silicon material; and
said plasma etch method uses an etchant gas composition comprising a chlorine containing etchant gas, a fluorine containing etchant gas, an oxygen containing etchant gas and a nitrogen containing etchant gas.

### Claim 6

A method for fabricating a semiconductor structure comprising:
forming a first gate stack upon a first region of a semiconductor substrate, said first gate stack comprising a first gate dielectric and a first metal gate material layer;
forming a material stack of a dielectric material layer and a second metal gate material layer, said dielectric material layer including a second gate dielectric and an etch stop layer that comprise a same material or a related material that is deposited or thermally grown, wherein said second gate dielectric is formed upon a second region of said semiconductor substrate that is laterally adjacent to said first region, and said etch stop layer is formed on sidewalls and a top surface of said first gate stack;
forming a block mask over said second gate dielectric;
removing portions of said second metal gate material layer and said etch stop layer from above a top surface of said first metal gate material layer while said block mask protects another portion of said second metal gate material layer overlying said second gate dielectric, wherein topmost surfaces of remaining portions of said second metal gate material layer and said second gate dielectric are formed above a first horizontal plane including a bottom surface of said first gate stack and below a second horizontal plane including a top surface of said first gate stack, and a remaining portion of said second gate dielectric is in physical contact with said first gate stack;
forming a silicon gate material layer upon said first gate stack and upon said second gate dielectric after said removal of said portions of said second metal gate material layer and said etch stop layer;
forming a planarizing layer upon said silicon gate material layer; and
etching non-selectively, while a vertical portion of said material stack that includes a vertical portion of said second metal gate material layer is present on a sidewall surface of a remaining portion said first metal gate material layer, said planarizing layer and said silicon gate material layer to form a second gate stack laterally adjacent said first gate stack while using said etch stop layer as an etch indicator layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising patterning said first gate stack and said second gate stack to form a first gate over said first region of said semiconductor substrate and a second gate over said second region of said semiconductor substrate, respectively.

### Claim 8 (depends on 6)

The method of claim 6, wherein said first region comprises a first orientation surface semiconductor layer having a first crystallographic orientation, and said second region comprises a second orientation surface semiconductor layer having a second crystallographic orientation different from said first crystallographic orientation.

### Claim 9 (depends on 6)

The method of claim 6, wherein said etching non-selectively uses a plasma etch method.

### Claim 10 (depends on 6)

The method of claim 6, wherein:
said planarizing layer comprises an organic polymer material;
said silicon gate material layer comprises at least a silicon material; and
said plasma etch method uses an etchant gas composition comprising a chlorine containing etchant gas, a fluorine containing etchant gas, an oxygen containing etchant gas and a nitrogen containing etchant gas.

### Claim 11

A method for fabricating a semiconductor structure comprising:
forming a first gate stack upon a first region of a semiconductor substrate, said first gate stack comprising a first gate material layer;
forming a material stack of a dielectric material layer and a metal gate material layer, said dielectric material layer including an etch stop layer and a second gate dielectric, wherein said etch stop layer is formed on a top surface and a sidewall surface of said first gate material layer, and said second gate dielectric is formed upon said first gate stack and a laterally adjacent second region of said semiconductor substrate;
forming a block mask over said second gate dielectric;
removing portions of said metal gate material layer and said etch stop layer from above a top surface of said first gate material layer while said block mask protects another portion of said metal gate layer overlying said second gate dielectric, wherein topmost surfaces of remaining portions of said metal gate material layer and said second gate dielectric are formed above a first horizontal plane including a bottom surface of said first gate stack and below a second horizontal plane including a top surface of said first gate stack, and a remaining portion of said second gate dielectric is in physical contact with said first gate stack;
forming a second gate material layer upon said first gate stack and upon said second gate dielectric after said removal of said portions of said metal gate layer and said etch stop layer;
forming a planarizing layer upon said second gate material layer; and
simultaneously etching non-selectively, while a vertical portion of said material stack that includes a vertical portion of said metal gate material layer is present on a sidewall surface of a remaining portion of said first gate material layer, said planarizing layer and said second gate material layer while said etch stop layer is present on said top surface and said sidewall surface of said first gate material layer, to form a second gate stack laterally adjacent said first gate stack, wherein said etch stop layer serves as an etchback indicator layer during said simultaneous etching.

### Claim 12 (depends on 11)

The method of claim 11, further comprising patterning said first gate stack and said second gate stack to form a first gate over said first region of said semiconductor substrate and a second gate over said second region of said semiconductor substrate.

### Claim 13 (depends on 11)

The method of claim 11, wherein said first region comprises a first crystallographic orientation and said second region comprises a second crystallographic orientation different from said first crystallographic orientation.

### Claim 14 (depends on 11)

The method of claim 11, wherein said etching non-selectively uses a plasma etch method.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
said planarizing layer comprises an organic polymer material;
said second gate material layer comprises at least a silicon material; and
said plasma etch method uses an etchant gas composition comprising a chlorine containing etchant gas, a fluorine containing etchant gas, an oxygen containing etchant gas and a nitrogen containing etchant gas.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
forming a first gate dielectric prior to forming said first gate material layer; and
forming a second gate dielectric after forming said first gate material layer and concurrently with formation of said etch stop layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein said etch stop layer and said second gate dielectric are contiguous with each other.

### Claim 18 (depends on 16)

The method of claim 16, wherein said etch stop layer and said second gate dielectric include a same dielectric material.

### Claim 19 (depends on 11)

The method of claim 11, wherein said first material layer includes a first silicon gate material layer.

### Claim 20 (depends on 11)

The method of claim 11, wherein said first material layer includes a first metal gate material layer comprising a metal gate material.