# US 8,785,280 B2 · Super-self-aligned Trench-DMOS structure and method

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- Number: US 8,785,280 B2
- Document ID: US8785280B2
- Status: Granted
- Kind: B2
- Application number: 13/709,614
- Filed: 2012-12-10
- Published: 2014-01-02
- Granted: 2014-07-22
- Earliest claimed: 2008-08-08
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: François Hébert
- Web page: https://patentgrep.com/patent/US8785280B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/154: {Dispositions}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.

## Claims

### Claim 1

A method for manufacturing a vertical semiconductor device comprising:
a) forming a body layer in an epitaxial layer wherein the epitaxial layer is of a first semiconductor type and the body layer is of a second semiconductor type;
b) forming a trench in the epitaxial layer;
c) lining a bottom and one or more sidewalls of the trench with a gate insulating layer;
d) forming a gate electrode in the trench in the body layer and epitaxial layer, wherein a gate oxide is disposed between the gate electrode and the body layer and between the gate electrode and the epitaxial layer;
e) forming a cap insulator over the gate electrode;
f) etching back around the cap insulator such that the top of the gate electrode is even with or protrudes above a surface of the epitaxial layer;
g) forming a spacer on the epitaxial layer self-aligned to the cap insulator, wherein the spacer includes a heavy concentration of dopants of the first semiconductor type and wherein the spacer is self-aligned to the cap insulating layer, and wherein forming the spacer comprises depositing a layer of material and then anisotropically etching back the layer of material with an etch selective to the insulator cap such that only the spacer is left and the body layer next to the spacer is etched back below the bottom of the spacer;
h) diffusing at least a portion of the dopants of the spacer into the body layer to form a source region below the spacer wherein the source region is of the first semiconductor type;
i) implanting a body contact region containing dopants of a second semiconductor type in the body layer and annealing the body contact region, wherein implanting a body contact region is self-aligned to the spacer; and
j) forming a metal layer over the insulator cap, spacer, source region and body contact region.

### Claim 2 (depends on 1)

The method of claim 1 wherein h) is performed the same time as annealing the body contact region in i).

### Claim 3 (depends on 1)

The method of claim 1 wherein h) is performed after depositing the layer of material in g), but before anisotropically etching in g).

### Claim 4 (depends on 1)

The method of claim 1 wherein h) is performed the same time as annealing the body contact region in i).

### Claim 5 (depends on 1)

The method of claim 1, wherein g) further comprises anisotropic etching such that the body layer next to the spacer is etched back to a level of a bottom of the source region of the finished device.

### Claim 6 (depends on 1)

The method of claim 1, wherein d) includes forming the gate electrode such that at least a portion of the gate electrode protrudes above a surface of the epitaxial layer.

### Claim 7 (depends on 6)

The method of claim 6 wherein f) includes etching back the epitaxial layer such that at least a portion of the gate electrode protrudes above a surface of the epitaxial layer.

### Claim 8 (depends on 6)

The method of claim 6 wherein b) includes forming a thin oxide layer on the epitaxial layer; forming a nitride layer on top of the thin oxide layer; forming a thick oxide layer on top of the nitride layer; and etching the epitaxial layer through one or more openings in the thick oxide layer, nitride layer and thin oxide layer to form the trench; and wherein d) includes depositing conductive material in the trench wherein the gate oxide is disposed between the conductive material and the epitaxial layer; and etching the thick oxide layer down to the nitride layer leaving a portion of the conductive material protruding above an exposed surface of the nitride layer; and wherein e) includes oxidizing the portion of the conductive material protruding above an exposed surface of the nitride layer.

### Claim 9 (depends on 1)

The method of claim 1 wherein the first semiconductor type is N-type, and the second semiconductor type is P-type.

### Claim 10 (depends on 1)

The method of claim 1 wherein the first semiconductor type is P-type, and the second semiconductor type is N-type.

### Claim 11 (depends on 1)

The method of claim 1 wherein a) is performed after f).

### Claim 12 (depends on 1)

The method of claim 1 wherein b) includes forming a hardmask oxide;
d) includes forming a conductor layer that protrudes above the top of the epitaxial layer; wherein e) includes forming an cap insulator comprising nitride; and wherein
f) includes selectively etching away the hardmask oxide.

### Claim 13 (depends on 1)

The method of claim 1, wherein the spacer is made of polysilicon.