# US 8,785,279 B2 · High voltage field balance metal oxide field effect transistor (FBM)

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,785,279 B2
- Document ID: US8785279B2
- Status: Granted
- Kind: B2
- Application number: 13/561,523
- Filed: 2012-07-30
- Published: 2014-01-30
- Granted: 2014-07-22
- Earliest claimed: 2012-07-30
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Anup Bhalla; Hamza Yilmaz; Madhur Bobde; Lingpeng Guan; Jun Hu; Jongoh Kim; Yongping Ding
- Inventors: Anup Bhalla; Hamza Yilmaz; Madhur Bobde; Lingpeng Guan; Jun Hu; Jongoh Kim; Yongping Ding
- Web page: https://patentgrep.com/patent/US8785279B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/058: {by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01: Manufacture or treatment
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
a) providing a semiconductor substrate of a first conductivity type;
b) forming an epitaxial layer of the first conductivity type on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;
c) forming body regions of a second conductivity type that is opposite of the first conductivity type near the top surface of the surface shielded region;
d) forming source regions of the first conductivity type near the top surface of the surface shielded region;
e) forming a plurality of gates on the top surface of the surface shielded region;
f) forming a drain on a bottom surface of the semiconductor substrate;
g) forming a plurality of trenches in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region;
h) forming a plurality of buried doped regions of the second conductivity type, whereby each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region; and
i) forming one or more charge linking paths of the second conductivity type along one or more trench walls of the plurality of trenches and configured to electrically connect a buried doped region to the body region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the surface shielded region is configured to support approximately one-third of the breakdown voltage (BV) and the voltage blocking region is configured to support approximately two-thirds of the BV.

### Claim 3 (depends on 2)

The method of claim 2, wherein the buried doped region is configured to support approximately one-half of the BV supported by the surface shielded region and the trench insulation material supports the remainder of the BV supported by the surface shielded region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the trench filling material in some of the trenches is insulated from the source electrode and is electrically connected to the gate electrode.

### Claim 5 (depends on 1)

The method of claim 1, wherein a doping concentration of the surface shielded region is between 5 and 100 times greater than a doping concentration of the voltage blocking region.

### Claim 6 (depends on 1)

The method of claim 1, wherein the trench filling material is polysilicon.

### Claim 7 (depends on 1)

The method of claim 1, wherein the trench insulation material is an oxide material.

### Claim 8 (depends on 1)

The method of claim 1, wherein a doping concentration of the charge linking region is lower than the doping concentration of the body region.

### Claim 9 (depends on 1)

The method of claim 1, wherein the trench insulation material is of substantially uniform thickness.

### Claim 10 (depends on 1)

The method of claim 1, wherein the trench insulation material is thicker at the bottom of the trenches.

### Claim 11 (depends on 1)

The method of claim 1, wherein the trench insulation material is thickness is tapered higher near the trench bottom.

### Claim 12 (depends on 1)

The method of claim 1, wherein the charge linking paths are formed by implanting dopants of the second conductivity type along one or more trench walls of one or more of the plurality of trenches.

### Claim 13 (depends on 1)

The method of claim 1, wherein the charge linking paths are formed by:
a) forming a first portion of the surface shielded region on the voltage blocking region;
b) implanting dopants of the second conductivity type into the top surface of the first portion of the surface shielded region at one or more selected locations; and
c) forming a second portion of the surface shielded region above the first portion and the implanted dopants.

### Claim 14 (depends on 1)

The method of claim 1, wherein each of the plurality of buried doped regions is connected to the source region by one of the one or more charge linking paths.

### Claim 15 (depends on 14)

The method of claim 14, wherein the charge linking paths are formed by implanting dopants of the second conductivity type along one or more of the trench walls of each of the plurality of trenches.

### Claim 16 (depends on 14)

The method of claim 14, wherein the charge linking paths are formed by the growth of an epitaxial layer along one or more of the trench walls of each one of the plurality of trenches.

### Claim 17 (depends on 14)

The method of claim 14, wherein the charge linking paths are formed by:
a) forming the voltage blocking region and a first portion of the surface shielded region;
b) implanting dopants of the second conductivity type into the top surface of the surface shielded region at a location where each of the plurality of trenches will be formed; and
c) forming a second portion of the surface shielded region above the voltage blocking region and the implanted dopants.

### Claim 18

A method of manufacturing a semiconductor device, comprising:
a) forming an epitaxial layer of the first conductivity type on a top surface of a semiconductor substrate of a first conductivity type, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;
b) forming a plurality of buried doped regions of the second conductivity type, whereby each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region;
c) forming one or more charge linking paths of the second conductivity type along one or more trench walls of the plurality of trenches;
d) lining the trenches are lined with a trench insulation material;
e) filling remaining portions of the trenches with an electrically conductive trench filling material;
f) forming body regions of a second conductivity type that is opposite of the first conductivity type near the top surface of the surface shielded region, wherein the one or more charge linking paths are configured to electrically connect the buried doped regions to the body regions;
f) forming source regions of the first conductivity type near the top surface of the surface shielded region, wherein the trench filling material is configured to be in electrical contact with the source regions;
g) forming a plurality of gates on the top surface of the surface shielded region.