# US 8,785,277 B2 · Method of manufacturing the trench power semiconductor structure

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- Number: US 8,785,277 B2
- Document ID: US8785277B2
- Status: Granted
- Kind: B2
- Application number: 13/617,645
- Filed: 2012-09-14
- Published: 2013-12-12
- Granted: 2014-07-22
- Earliest claimed: 2012-06-08
- Assignees: Super Group Semiconductor Co., Ltd.
- Applicants: Hsiu-Wen Hsu
- Inventors: Hsiu-Wen Hsu
- Web page: https://patentgrep.com/patent/US8785277B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a trench power semiconductor structure is provided. The method comprising the steps of: providing a base, forming a dielectric pattern layer on the base to define an active region and a terminal region, wherein a portion of the base in the active region and the terminal region is covered by the dielectric pattern layer; selectively forming a first epitaxial layer on the base without being covered by the dielectric pattern layer; removing the dielectric pattern layer in the active region to form a gate trench on the base, and forming a gate dielectric layer on the first epitaxial layer and on the inner surface of the gate trench; forming the gate structure in the gate trench; utilizing the dielectric pattern layer to forming a body on or in the first epitaxial layer; and forming a source on the upper portion of the body.

## Claims

### Claim 1

A method of manufacturing the trench power semiconductor structure, comprising:
providing a base;
forming a dielectric pattern layer on the base to define an active region and a terminal region, wherein a portion of the base in the active region and the terminal region is covered by the dielectric pattern layer;
selectively forming a first epitaxial layer on the base without being covered by the dielectric pattern layer;
removing the dielectric pattern layer in the active region to form at least a gate trench on the base;
forming a gate dielectric layer in the gate trench and on the first epitaxial layer;
forming a gate structure in the gate trench;
utilizing the dielectric pattern layer in the terminal region as a mask to form a body in or on the first epitaxial layer; and
forming a source on the upper portion of the body.

### Claim 2 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein before the step of forming the gate dielectric layer in the gate trench, the method of manufacturing the trench power semiconductor structure further comprising: etching the bottom of the gate trench.

### Claim 3 (depends on 2)

The method of manufacturing the trench power semiconductor structure of claim 2, wherein after the step of etching the bottom of the gate trench and before the step of forming the gate dielectric layer in the gate trench, the method of manufacturing the trench power semiconductor structure further comprising: forming a sacrificial oxide layer inside the gate trench and on the base.

### Claim 4 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein, the body is formed in the first epitaxial layer by using an ion implantation manner.

### Claim 5 (depends on 4)

The method of manufacturing the trench power semiconductor structure of claim 4, wherein, the source is formed on the upper portion of the body by using the ion implantation manner.

### Claim 6 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein, the body is formed on the first epitaxial layer by using an epitaxial manner.

### Claim 7 (depends on 6)

The method of manufacturing the trench power semiconductor structure of claim 6, wherein, the source is formed on the upper portion of the body by using an ion implantation manner.

### Claim 8 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein, the thickness of the first epitaxial layer is larger than that of the gate dielectric layer.

### Claim 9 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein, the steps of forming the body and the source are proceeded after the step of forming the gate dielectric layer.

### Claim 10 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein, the dielectric pattern layer comprises a bottom dielectric structure, an isolating structure and a shielding structure.

### Claim 11 (depends on 10)

The method of manufacturing the trench power semiconductor structure of claim 10, wherein, the thickness of the first epitaxial layer is larger than that of the bottom dielectric structure.

### Claim 12 (depends on 1)

The method of manufacturing the trench power semiconductor structure of claim 1, wherein the first epitaxial layer is formed by the selective epitaxial growth manner.