# US 8,785,274 B2 · Method for manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,274 B2 - Document ID: US8785274B2 - Status: Granted - Kind: B2 - Application number: 12/785,964 - Filed: 2010-05-24 - Published: 2010-12-02 - Granted: 2014-07-22 - Earliest claimed: 2009-06-01 - Assignees: Fujitsu Semiconductor Limited - Applicants: Katsuyoshi Matsuura; Masayoshi Asano; Hiroyuki Ogawa; Myounggoo Lee - Inventors: Katsuyoshi Matsuura; Masayoshi Asano; Hiroyuki Ogawa; Myounggoo Lee - Web page: https://patentgrep.com/patent/US8785274B2 ## CPC - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/038: {the capacitor being in a trench in the substrate} - H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells} - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/716: {having vertical extensions} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/0217: {forming self-aligned punch-through stoppers or threshold implants under gate regions} - H10D 62/299: {having lateral doping variations (IGFETs having lightly doped source or drain extensions H10D30/601)} - H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate having a first region and a second region as a part of a surface layer of the semiconductor substrate, the first region and the second region being a first electrical conduction type, the first region and the second region being isolated by an element isolation insulating film, a first gate electrode and a capacitor structure being disposed on the first region, a second gate electrode being disposed on the second region, the first region not including an area on the element isolation insulating film; forming a first insulating film covering the first gate electrode, the second gate electrode, and the capacitor structure and covering the surface of the semiconductor substrate; forming a first mask covering the second gate electrode and a third region, the third region being around the second gate electrode in the surface layer of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a doped region of the second electrical conduction type in each of a fourth region and a fifth region in the surface layer of the semiconductor substrate, the fourth region being a region between the first gate electrode and the capacitor structure, the fifth region being a region opposite to the capacitor structure with the first gate electrode therebetween; removing the first mask, so as to expose the first insulating film present under the first mask; forming first side walls on the first gate electrode and forming second side walls on the second gate electrode by etching the first insulating film; and implanting a second impurity of the second electrical conduction type into the third region after forming a second mask covering the fourth region and the fifth region. ### Claim 2 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein after the implanting a second impurity, the method further comprising: forming a second insulating film covering the first gate electrode provided with the first side walls and the capacitor structure and covering the surface of the semiconductor substrate; and leaving a second insulating portion on the first side walls by etching the second insulating film. ### Claim 3 (depends on 2) The method for manufacturing a semiconductor device according to claim 2, wherein the second insulating portion covers the first gate electrode provided with the first side walls, and the capacitor structure and covers the surface of the semiconductor substrate. ### Claim 4 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the peak concentration of a depth-direction profile of the first impurity is lower than the peak concentration of a depth-direction profile of the second impurity. ### Claim 5 (depends on 4) The method for manufacturing a semiconductor device according to claim 4, wherein the deepest position of a depth-direction profile of the first impurity is deeper than the deepest position of a depth-direction profile of the second impurity. ### Claim 6 (depends on 4) The method for manufacturing a semiconductor device according to claim 4, wherein the acceleration energy of the first impurity in the implanting of the first impurity is within the range of 6 times to 14 times the acceleration energy of the second impurity in the implanting of the second impurity. ### Claim 7 (depends on 4) The method for manufacturing a semiconductor device according to claim 4, wherein the first impurity and the second impurity are the same type of impurity. ### Claim 8 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed having a thickness within the range of 5 nm to 20 nm. ### Claim 9 (depends on 8) The method for manufacturing a semiconductor device according to claim 8, wherein the material for the first insulating film is silicon oxide. ### Claim 10 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein before the forming of the first insulating film, the method further comprising: implanting a fourth impurity of the first electrical conduction type into the second region and the third region slantingly while the first gate electrode and the capacitor structure are masked. ### Claim 11 (depends on 10) The method for manufacturing a semiconductor device according to claim 10, wherein the fourth impurity is implanted into the semiconductor substrate slantingly from a plurality of directions by rotating the semiconductor substrate. ### Claim 12 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein a part of the capacitor structure is provided on the first region and a remaining part of the capacitor structure is provided on the element isolation insulating film. ### Claim 13 A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region in the surface layer of the semiconductor substrate, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween; and forming first side walls on the first gate electrode by etching the first insulating film, wherein the semiconductor substrate is further provided with an element isolation groove as a lower portion of the capacitor structure, and the capacitor structure is formed on the semiconductor substrate while extending from the element isolation groove to the first gate electrode side. ### Claim 14 (depends on 13) The method for manufacturing a semiconductor device according to claim 13, wherein the semiconductor substrate is further provided with a sixth region, which is formed opposing to the first gate electrode with the element isolation groove therebetween and which is of the first electrical conduction type, a third gate electrode is formed on the sixth region, and the capacitor structure is formed on the semiconductor substrate while extending from the element isolation groove to the third gate electrode side. ### Claim 15 (depends on 13) The method for manufacturing a semiconductor device according to claim 13, wherein a part of the capacitor structure is provided on the first region and a remaining part of the capacitor structure is provided on the element isolation insulating film.