# US 8,785,273 B2 · FinFET non-volatile memory and method of fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,273 B2 - Document ID: US8785273B2 - Status: Granted - Kind: B2 - Application number: 13/444,219 - Filed: 2012-04-11 - Published: 2013-10-17 - Granted: 2014-07-22 - Earliest claimed: 2012-04-11 - Assignees: International Business Machines Corporation - Applicants: Kangguo Cheng; Bruce B. Doris; Ali Khakifirooz; Pranita Kulkarni - Inventors: Kangguo Cheng; Bruce B. Doris; Ali Khakifirooz; Pranita Kulkarni - Web page: https://patentgrep.com/patent/US8785273B2 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/30: characterised by the memory core region - H10B 43/35: with cell select transistors, e.g. NAND - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/0411: {of FETs having floating gates} - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)} - H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} - H10D 30/6893: {wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate} - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate} - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10D 64/037: {comprising charge-trapping insulators} - H10D 84/0158: {the components including FinFETs} - H10D 86/011: {comprising FinFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer. ## Claims ### Claim 1 A method of manufacturing a FinFET non-volatile memory device, comprising: providing a substrate; depositing a layer of a semiconductor material over said substrate; depositing a first dielectric layer on top of said semiconductor layer; patterning said semiconductor layer and said first dielectric layer to form a fin structure; depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall; damaging said charge storage layer on said first sidewall and top surface by an angled ion implantation process; etching said damaged charged storage layer until it is substantially removed; forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer; depositing a second dielectric material over said device, wherein said fin and gate structures are completely covered; opening contact holes in said second dielectric material directly over said fin structure, exposing said first dielectric layer; etching said first dielectric layer until it is substantially removed; implanting dopants through said contact holes to form source and drain regions; and filling said contact holes with a metal. ### Claim 2 (depends on 1) The method according to claim 1, further comprising polishing the surface of said device by chemical mechanical polishing. ### Claim 3 (depends on 1) The method according to claim 1 wherein said substrate comprises an insulating layer overlying a semiconductor layer. ### Claim 4 (depends on 1) The method according to claim 1, wherein said first and second gate structures each comprise a gate dielectric and a gate electrode; wherein for said first gate structure, said gate dielectric is adjacent to said first sidewall and said first gate electrode is adjacent to said gate dielectric; and wherein for said second gate structure, said gate dielectric is adjacent to said charge storage layer and said second gate electrode is adjacent to said gate dielectric. ### Claim 5 (depends on 1) The method according to claim 1 wherein said substrate comprises an insulating layer overlying a semiconductor layer. ### Claim 6 A method of manufacturing a FinFET non-volatile memory device, comprising: providing a substrate; depositing a layer of a semiconductor material over said substrate; depositing a first dielectric layer on top of said semiconductor layer; patterning said semiconductor layer and said first dielectric layer to form a fin structure; depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall; damaging said charge storage layer on said first sidewall and top surface by an angled ion implantation process; etching said damaged charged storage layer until it is substantially removed; and forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer, wherein said first and second gate structures each comprise a gate dielectric and a gate electrode; wherein for said first gate structure, said gate dielectric is adjacent to said first sidewall and said first gate electrode is adjacent to said gate dielectric; and wherein for said second gate structure, said gate dielectric is adjacent to said charge storage layer and said second gate electrode is adjacent to said gate dielectric. ### Claim 7 (depends on 6) The method according to claim 6, further comprising polishing the surface of said device by chemical mechanical polishing. ### Claim 8 (depends on 6) The method according to claim 6 wherein said substrate comprises an insulating layer overlying a semiconductor layer. ### Claim 9 A method of manufacturing a FinFET non-volatile memory device, comprising: providing a substrate; depositing a layer of a semiconductor material over said substrate; depositing a first dielectric layer on top of said semiconductor layer; patterning said semiconductor layer and said first dielectric layer to form a fin structure; depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall; damaging said charge storage layer on said first sidewall and top surface by an angled ion implantation process; etching said damaged charged storage layer until it is substantially removed; and forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer, wherein said charge storage layer comprises a charge storage stack selected from the group consisting of: dielectric/poly-silicon/dielectric, silicon dioxide/silicon nitride/silicon dioxide, silicon dioxide/high-k dielectric/silicon dioxide, and a dielectric that contains nanoparticles. ### Claim 10 (depends on 9) The method according to claim 9, further comprising polishing the surface of said device by chemical mechanical polishing. ### Claim 11 (depends on 9) The method according to claim 9 wherein said substrate comprises an insulating layer overlying a semiconductor layer. ### Claim 12 A method of manufacturing a FinFET non-volatile memory device, comprising: providing a substrate; depositing a layer of a semiconductor material over said substrate; depositing a first dielectric layer on top of said semiconductor layer; patterning said semiconductor layer and said first dielectric layer to form a fin structure; depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall; depositing a second dielectric layer over said charge storage layer; damaging said second dielectric layer on said first sidewall and top surface by an angled ion implantation process; etching said damaged second dielectric layer until it is substantially removed, exposing portions of said charge storage layer; etching said exposed portions of said charge storage layer until they are substantially removed; etching said remaining second dielectric layer until it is substantially removed; and, forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: depositing a third dielectric material over said device, wherein said fin and gate structures are completely covered; opening contact holes in said third dielectric material directly over said fin structure, exposing said first dielectric layer; etching said first dielectric layer until it is substantially removed; implanting dopants through said contact holes to form source and drain regions; and filling said contact holes with a metal. ### Claim 14 (depends on 13) The method according to claim 13, further comprising polishing said contact holes by chemical mechanical polishing. ### Claim 15 (depends on 12) The method according to claim 12, wherein said first and second gate structures each comprise a gate dielectric and a gate electrode; wherein for said first gate structure, said gate dielectric is adjacent to said first sidewall and said first gate electrode is adjacent to said gate dielectric; and wherein for said second gate structure, said gate dielectric is adjacent to said charge storage layer and said second gate electrode is adjacent to said gate dielectric. ### Claim 16 (depends on 12) The method according to claim 12, wherein said charge storage layer comprises a charge storage stack selected from the group consisting of: dielectric/poly-silicon/dielectric, silicon dioxide/silicon nitride/silicon dioxide, silicon dioxide/high-k dielectric/silicon dioxide, and a dielectric that contains nanoparticles. ### Claim 17 (depends on 12) The method according to claim 12 wherein said substrate comprises an insulating layer overlying a semiconductor layer.