# US 8,785,272 B2 · Process to make high-K transistor dielectrics

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- Number: US 8,785,272 B2
- Document ID: US8785272B2
- Status: Granted
- Kind: B2
- Application number: 13/224,059
- Filed: 2011-09-01
- Published: 2011-12-29
- Granted: 2014-07-22
- Earliest claimed: 2002-04-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Liang-Gi Yao; Ming-Fang Wang; Shih-Chang Chen; Mong-Song Liang
- Inventors: Liang-Gi Yao; Ming-Fang Wang; Shih-Chang Chen; Mong-Song Liang
- Web page: https://patentgrep.com/patent/US8785272B2

## CPC

- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- C23C 16/56: After-treatment
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/6529: {by exposure to a gas or vapour}
- H10P 14/6929: {the material containing aluminium, e.g. AlSiOx}
- H10P 14/6932: {the material containing titanium, e.g. TiSiOx}
- H10P 14/6934: {the material containing zirconium, e.g. ZrSiOx}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

## Claims

### Claim 1

A method of reducing impurities in a high-k dielectric layer, comprising the steps of:
providing a substrate;
forming a high-k dielectric layer having impurities therein; the high-k dielectric layer being formed by a process that introduces the impurities into the high-k dielectric layer;
annealing the high-k dielectric layer to reduce the impurities within the high-k dielectric layer, wherein annealing the high-k dielectric layer is performed in an ambient selected from the group consisting of H2, H2/N2, O2/N2, He, and Ar to avoid additional oxidation of the high-k dielectric layer; and
forming a gate layer upon the annealed high-k dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1,
wherein the substrate is a silicon substrate;
wherein the high-k dielectric layer is a metal oxide or a metal silicate;
wherein the process is an MOCVD process; and
wherein the impurities in the high-k dielectric layer include carbon impurities.

### Claim 3 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer is comprised of a material selected from the group consisting of HfO2, ZrO2, La2O3, Y2O3, Al2O3, TiO2, HfSixOy, ZrSixOy, LaSixOy, YSixOy, AlSixOy, and TiSixOy.

### Claim 4 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer is comprised of a material selected from the group consisting of HfO2, ZrO2, Al2O3, HfSixOy and ZrSixOy.

### Claim 5 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is a rapid thermal anneal conducted at a temperature of from about 280 to 820° C. for from about 0.5 to 300 seconds.

### Claim 6 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is a rapid thermal anneal conducted at a temperature of from about 300 to 800° C. for from about 2 to 100 seconds.

### Claim 7 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is a furnace anneal process conducted at a temperature of from about 300 to 800° C. for from about 5 to 300 minutes.

### Claim 8 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either rapid thermal processing or a furnace anneal process.

### Claim 9 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either a rapid thermal processing or a furnace anneal process using an ambient selected from the group consisting of H2/N2 and O2/N2.

### Claim 10 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is conducted at a temperature of from about 280 to 820° C. using either rapid thermal processing or a furnace anneal process.

### Claim 11 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer anneal is conducted at a temperature of from about 300 to 800° C. using either rapid thermal processing or a furnace anneal process with an ambient selected from the group consisting of H2/N2 and O2/N2.

### Claim 12 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer has a thickness of from about 5 to 200 Å.

### Claim 13 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer has a thickness of from about 20 to 100 Å.

### Claim 14 (depends on 1)

The method of claim 1, wherein the gate layer comprised of a material selected from the group consisting of polysilicon, TaN/W, TiN/W, TaN/Al and TiN/Al.

### Claim 15 (depends on 1)

The method of claim 1, wherein the gate layer is comprised of polysilicon.

### Claim 16 (depends on 1)

The method of claim 1, wherein the gate layer has a thickness of from about 100 to 3000 Å.

### Claim 17 (depends on 1)

The method of claim 1, wherein the gate layer has a thickness of from about 500 to 2000 Å.

### Claim 18 (depends on 1)

The method of claim 1,
wherein the process is an ALCVD process; and
wherein the impurities in the high-k dielectric layer include chlorine impurities.