# US 8,785,271 B2 · DRAM cell based on conductive nanochannel plate

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- Number: US 8,785,271 B2
- Document ID: US8785271B2
- Status: Granted
- Kind: B2
- Application number: 13/017,682
- Filed: 2011-01-31
- Published: 2012-08-02
- Granted: 2014-07-22
- Earliest claimed: 2011-01-31
- Assignees: Globalfoundries Inc.
- Applicants: Dmytro Chumakov; Wolfgang Buchholtz; Petra Hetzer
- Inventors: Dmytro Chumakov; Wolfgang Buchholtz; Petra Hetzer
- Web page: https://patentgrep.com/patent/US8785271B2

## CPC

- H10B 12/33: {the capacitor extending under the transistor}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 12/033: {the capacitor extending over the transistor}
- H10D 1/716: {having vertical extensions}
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

## Claims

### Claim 1

A method comprising:
forming a source contact through a first inter layer dielectric (ILD);
forming a conductive body on the first ILD;
forming a second ILD on the conductive body;
forming drain and gate contacts through the second ILD, conductive body, and first ILD;
forming nano channels in the conductive body;
forming an insulating layer in the channels; and
metalizing the channels.

### Claim 2 (depends on 1)

The method according to claim 1, comprising forming the drain and gate contacts by:
forming first openings through the second ILD and conductive body;
forming an insulating liner in the first openings;
forming a second opening through the first ILD; and
filling the first and second openings with metal.

### Claim 3 (depends on 2)

The method according to claim 2, comprising forming the first openings by:
forming a mask on the second ILD; and
etching the second ILD and conductive body through the mask.

### Claim 4 (depends on 2)

The method according to claim 2, comprising forming the insulating liner of silicon oxide or a high-k oxide.

### Claim 5 (depends on 4)

The method according to claim 4, comprising forming the insulating liner to a thickness less than 5 nanometers (nm).

### Claim 6 (depends on 3)

The method according to claim 3, comprising forming the first ILD of a material that has etch selectivity with the conductive body.

### Claim 7 (depends on 6)

The method according to claim 6, comprising:
forming the conductive body of doped polysilicon; and
forming the first ILD of silicon nitride.

### Claim 8 (depends on 1)

The method according to claim 1, comprising forming the nano channels by:
forming an opening through the second ILD; and
forming an opening in the conductive body.

### Claim 9 (depends on 8)

The method according to claim 8, comprising forming the openings by:
forming a nano patterning mask on the second ILD;
etching the second ILD through the nano patterning mask;
partially etching the conductive body through the nano patterning mask; and
removing the nano patterning mask.

### Claim 10 (depends on 9)

The method according to claim 9, comprising etching the conductive body to a depth of 80% to 90% of the thickness of the conductive body.

### Claim 11 (depends on 9)

The method according to claim 9, comprising forming the nano patterning mask having features with a pitch of 50 nanometers (nm) to 100 nm.

### Claim 12 (depends on 1)

The method according to claim 1, further comprising forming the insulating layer of a high-k material.

### Claim 13

A method comprising:
forming a first inter layer dielectric (ILD) on at least one transistor;
forming a source contact through the first ILD for each transistor;
forming a conductive body of doped polysilicon on the first ILD;
forming a second ILD on the conductive body;
forming a drain contact and a gate contact for each transistor through the second ILD, conductive body, and first ILD, and electrically insulating the drain and gate contacts from the conductive body with a silicon oxide or high-k oxide liner;
forming nano channels in the conductive body;
depositing an insulating layer in the nano channels; and
metalizing the channels.

### Claim 14 (depends on 13)

The method according to claim 13, comprising forming the nano channels by:
forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm;
etching the second ILD through the mask;
etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body; and
removing the mask.