# US 8,785,270 B2 · Integrating schottky diode into power MOSFET

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- Number: US 8,785,270 B2
- Document ID: US8785270B2
- Status: Granted
- Kind: B2
- Application number: 13/948,988
- Filed: 2013-07-23
- Published: 2013-11-21
- Granted: 2014-07-22
- Earliest claimed: 2011-05-02
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Yi Su; Daniel Ng; Anup Bhalla; Hong Chang; Jongoh Kim; John Chen
- Web page: https://patentgrep.com/patent/US8785270B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 8/60: Schottky-barrier diodes
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 30/665: {having edge termination structures}
- H10D 62/161: {of FETs having Schottky gates}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 84/156: {the built-in components being Schottky barrier diodes}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
a) forming a plurality of trenches on a substrate using a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and shield electrode pickup trenches located in a termination area outside an active area containing the active gate trenches, the gate runner/termination trenches including one or more trenches that define a mesa located in an area outside an active area containing the active gate trenches; forming asymmetric sidewalls in the one or more trenches that define the mesa, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered by the second mask;
b) forming a first conductive region in the one or more trenches that define the mesa;
c) forming an intermediate dielectric region and a termination protection region in the one or more trenches that define the mesa using a second mask;
d) forming a second conductive region in the one or more trenches that define the mesa;
e) forming a first electrical contact to the second conductive regions, forming a second electrical contact to the first conductive region in the shield electrode pickup trenches located in the termination area, and forming one or more Schottky diodes within a mesa formed between termination trenches in an area outside an active area containing the active gate trenches using a third mask.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
f) disposing a metal layer on the device; and
g) forming a source metal region and a gate metal region from the metal layer using a fourth mask.

### Claim 3 (depends on 1)

The method of claim 1, wherein the asymmetric sidewalls include a first sidewall and a second sidewall, and the first sidewall having a thicker oxide layer than the second sidewall, the first sidewall being closer to the one or more Schottky diodes.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming one or more Schottky diodes includes depositing barrier metal on an exposed surface of the mesa formed between termination trenches.

### Claim 5 (depends on 4)

The method of claim 4, wherein the exposed surface of the mesa is an exposed surface of a well formed within the mesa.

### Claim 6

A method for fabricating a semiconductor device, comprising:
a) forming a plurality of trenches on a substrate using a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and shield electrode pickup trenches located in a termination area outside an active area containing the active gate trenches, the gate runner/termination trenches including one or more trenches that define a mesa located in an area outside an active area containing the active gate trenches;
b) forming a first conductive region in the one or more trenches that define the mesa;
c) forming an intermediate dielectric region and a termination protection region in the one or more trenches that define the mesa using a second mask;
d) forming a second conductive region in the one or more trenches that define the mesa;
e) forming a first electrical contact to the second conductive regions, forming a second electrical contact to the first conductive region in the shield electrode pickup trenches located in the termination area, and forming one or more Schottky diodes within a mesa formed between termination trenches in an area outside an active area containing the active gate trenches using a third mask;
wherein forming a Schottky diode includes performing a deep pocket implant to form a doped shielding region below a Schottky junction associated with the Schottky diode.