# US 8,785,268 B2 · Memory system with Fin FET technology

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- Number: US 8,785,268 B2
- Document ID: US8785268B2
- Status: Granted
- Kind: B2
- Application number: 11/614,815
- Filed: 2006-12-21
- Published: 2008-06-26
- Granted: 2014-07-22
- Earliest claimed: 2006-12-21
- Assignees: Spansion LLC
- Applicants: Wei Zheng; Lei Xue; Kuo-Tung Chang
- Inventors: Wei Zheng; Lei Xue; Kuo-Tung Chang
- Web page: https://patentgrep.com/patent/US8785268B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.

## Claims

### Claim 1

A method for manufacturing a memory system comprising:
forming a vertical fin of a semiconductor substrate being a continuous layer, the vertical fin protruding vertically, and being part of the semiconductor substrate;
forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from the vertical fin;
forming a second insulator layer from the charge-storage layer;
removing at least portions of the first insulator layer, the charge storage layer and the second insulator layer from above the vertical fin such that the charge storage layer is isolated on both sides of the vertical fin; and
forming a gate over the vertical fin to thereby form a fin field effect transistor.

### Claim 2 (depends on 1)

The method as claimed in claim 1 wherein forming the charge-storage layer includes forming a silicon rich nitride layer.

### Claim 3 (depends on 1)

The method as claimed in claim 1 wherein the fin field effect transistor is a self aligned SONOS fin field effect transistor.

### Claim 4 (depends on 1)

The method as claimed in claim 1 wherein forming the second insulator layer includes steam oxidizing an outer portion of the charge-storage layer.

### Claim 5 (depends on 1)

The method as claimed in claim 1 further comprising:
forming a memory sub-system with the memory system; and
forming a device, a printed circuit board, or an electronic system with the memory sub-system.

### Claim 6

A method for manufacturing a memory system comprising:
forming a vertical fin of a semiconductor substrate being a continuous layer, the vertical fin protruding vertically, and being part of the semiconductor substrate and having a sloped sidewall substantially vertical, wherein the vertical fin is capped by an oxide layer, and the oxide layer is in direct contact with a word line;
forming a silicon rich nitride layer on a first dielectric layer including insulating the silicon rich nitride layer from the vertical fin, wherein the silicon rich nitride layer is a charge-storage layer;
steam oxidizing a second dielectric layer from the charge-storage layer; and
forming the word line over the vertical fin to thereby form a fin field effect transistor.

### Claim 7 (depends on 6)

The method as claimed in claim 6 wherein steam oxidizing the second dielectric layer on the charge-storage layer includes isolating the silicon rich layer from the word line.

### Claim 8 (depends on 6)

The method as claimed in claim 6 wherein the fin field effect transistor is a self aligned SONOS fin field effect transistor.

### Claim 9 (depends on 6)

The method as claimed in claim 6 wherein forming the silicon rich nitride layer includes forming a gradient concentration of silicon in the silicon rich nitride layer.

### Claim 10 (depends on 6)

The method as claimed in claim 6 further comprising patterning the word line on the second dielectric layer.

### Claim 11

A memory system comprising:
a semiconductor substrate being a continuous layer;
a vertical fin formed of the semiconductor substrate, the vertical fin protruding vertically, and being part of the semiconductor substrate;
a plurality of first insulator layers on both sides of the vertical fin;
a plurality of charge-storage layers on each of the first insulator layers, wherein the charge-storage layers are isolated on both sides of the vertical fin;
a plurality of second insulator layers on the charge-storage layers; and
a gate on the vertical fin.

### Claim 12 (depends on 11)

The system as claimed in claim 11 wherein the charge-storage layer includes a silicon rich nitride layer.

### Claim 13 (depends on 11)

The system as claimed in claim 11 further comprising a self aligned SONOS fin field effect transistor formed on the vertical fin.

### Claim 14 (depends on 11)

The system as claimed in claim 11 wherein the second insulator layer includes the charge-storage layer having an outer portion oxidized.

### Claim 15 (depends on 11)

The system as claimed in claim 11 further comprising:
a memory sub-system with the memory system; and
a device, a printed circuit board, or an electronic system with the memory sub-system.

### Claim 16 (depends on 11)

The system as claimed in claim 11 wherein:
the first insulator layers are first dielectric layers on the vertical fin;
the charge-storage layers are silicon rich nitride layers on the first insulator layers;
the second insulator layers are second dielectric layers from the charge-storage layers; and
the gate is a poly-silicon gate on the second dielectric layers.

### Claim 17 (depends on 16)

The system as claimed in claim 16 wherein the second dielectric layer on the charge-storage layer isolates the charge-storage layer from a word line.

### Claim 18 (depends on 16)

The system as claimed in claim 16 further comprising a self aligned SONOS fin field effect transistor.

### Claim 19 (depends on 16)

The system as claimed in claim 16 wherein the charge-storage layer includes the silicon rich nitride layer having a gradient concentration.

### Claim 20 (depends on 16)

The system as claimed in claim 16 further comprising a word line patterned on the second dielectric layer.

### Claim 21 (depends on 1)

The method of claim 1, further comprising:
forming the first insulator layer continuously on sidewalls and over the vertical fin.