# US 8,785,263 B2 · Thin-film transistor substrate and method of manufacturing the same

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- Number: US 8,785,263 B2
- Document ID: US8785263B2
- Status: Granted
- Kind: B2
- Application number: 13/652,967
- Filed: 2012-10-16
- Published: 2013-12-12
- Granted: 2014-07-22
- Earliest claimed: 2012-06-11
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Tae-Young Choi; Bo-Sung Kim
- Web page: https://patentgrep.com/patent/US8785263B2

## CPC

- H10D 86/0241: {using liquid deposition, e.g. printing}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 10/82: Electrodes
- H10K 71/621: {Providing a shape to conductive layers, e.g. patterning or selective deposition}
- H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate}
- H10K 71/135: {using ink-jet printing}
- H10K 85/221: {Carbon nanotubes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.

## Claims

### Claim 1

A method of manufacturing a thin-film transistor substrate, the method comprising:
providing a gate line, and a gate electrode connected to the gate line, on a base substrate;
providing an insulating layer on the base substrate having the gate line and the gate electrode thereon;
providing a data line and an electrode pattern on the base substrate having the insulating layer thereon, the data line extended in a direction crossing the gate line and the electrode pattern connected to the data line;
hydrophobic-treating a surface of the insulating layer by using the data line and the electrode pattern as a mask;
providing a source electrode and a drain electrode from the electrode pattern, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode;
providing a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes; and
providing a pixel electrode on the base substrate having the semi-conductor pattern thereon, the pixel electrode connected to the drain electrode.

### Claim 2 (depends on 1)

The method of claim 1, wherein the providing an electrode pattern comprises:
providing an electrode layer on the base substrate having the insulating layer thereon;
providing a sacrificing metal layer on the base substrate having the electrode layer thereon;
etching the sacrificing metal layer and the electrode layer by using a photo pattern as an etching mask, the photo pattern formed on the sacrificing metal layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the providing a source electrode and a drain electrode comprises:
removing a portion of the photo pattern to form a remaining pattern;
etching the sacrificing metal layer of the electrode pattern by using the remaining pattern as an etching mask to form sacrificing electrodes spaced apart from each other; and
using the sacrificing electrodes as an etching mask to etch the electrode layer of the electrode pattern.

### Claim 4 (depends on 3)

The method of claim 3,
wherein the photo pattern comprises a first thickness portion, and the remaining pattern comprises a second thickness portion which is thinner than the first thickness portion, and
wherein the second thickness portion of the remaining pattern is removed to expose the sacrificing metal layer at the gap.

### Claim 5 (depends on 3)

The method of claim 3, wherein the providing a source electrode and a drain electrode further comprises removing the sacrificing electrodes, after the etching the electrode layer of the electrode pattern.

### Claim 6 (depends on 1)

The method of claim 1, wherein the hydrophobic-treating a surface of the insulating layer comprises hydrophobic-treating a surface of the insulating layer exposed by the electrode pattern to form a first part of the insulating layer, and wherein a thickness of the first part is smaller than or substantially equal to a total thickness of the insulating layer, the first part having a hydrophobic property, and
wherein a portion of the insulating layer below the electrode pattern has a hydrophilic property.

### Claim 7 (depends on 6)

The method of claim 6, wherein the hydrophobic-treating a surface of the insulating layer exposed by the electrode pattern comprises treating the exposed insulating layer by fluorine plasma.

### Claim 8 (depends on 6)

The method of claim 6, wherein the thickness of the first part is smaller than the total thickness of the insulating layer, and a lower portion of the insulating material below the first part has the hydrophilic property.

### Claim 9 (depends on 1)

The method of claim 1, wherein the providing a semi-conductor pattern comprises:
depositing a semi-conductor solution on the base substrate having the source electrode and the drain electrode thereon; and
thermal-treating the deposited semi-conductor solution on the base substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein the semi-conductor solution covers the source electrode, the drain electrode and the gap between the spaced apart source and drain electrodes, and a portion of the semi-conductor solution spreads toward the data line.

### Claim 11 (depends on 1)

The method of claim 1, wherein the hydrophobic-treating a surface of the insulating layer comprises providing a hydrophobic pattern on a surface of the insulating layer exposed by the electrode pattern.

### Claim 12 (depends on 11)

The method of claim 11, wherein the hydrophobic pattern comprises a self-assembly monolayer.