# US 8,785,261 B2 · Microelectronic transistor having an epitaxial graphene channel layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,785,261 B2
- Document ID: US8785261B2
- Status: Granted
- Kind: B2
- Application number: 12/888,979
- Filed: 2010-09-23
- Published: 2012-03-29
- Granted: 2014-07-22
- Earliest claimed: 2010-09-23
- Assignees: Intel Corporation
- Applicants: Sean King
- Inventors: Sean King
- Web page: https://patentgrep.com/patent/US8785261B2

## CPC

- H10D 62/882: {Graphene}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3208: {Silicon carbide}
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- H10P 14/3446: {Transition metal elements; Rare earth elements}
- H10P 70/20: {Cleaning during device manufacture}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor.

## Claims

### Claim 1

A method of fabricating a transistor comprising:
providing a structural substrate comprising silicon;
forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer;
forming a graphene layer on the formation substrate comprising annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane to reduce and desorb surface oxides at temperatures of about 700-900° C. and forming the graphene layer by silicon volatization at temperature of about 950° C.;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and
forming a gate abutting the gate dielectric.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.

### Claim 5 (depends on 1)

The method of claim 1, further including doping an impurity into the silicon carbide layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the impurity comprises iron or vanadium.

### Claim 7

A method of forming a transistor comprising:
depositing a thermodynamically unstable XC carbide layer on a formation substrate comprising depositing amorphous germanium carbide on a (0001)6H-SiC substrate;
decomposing the XC carbide layer into an X component and carbon;
volatilizing the X component;
forming a graphene layer from the carbon;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and
forming a gate abutting the gate dielectric.

### Claim 8 (depends on 7)

The method of claim 7, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400° C., and wherein volatilizing the X component comprises sublimating germanium by heating to a temperature of about 980° C.

### Claim 9

A method of forming a transistor comprising:
depositing a thermodynamically unstable XC carbide layer on a formation substrate;
decomposing the XC carbide layer into an X component and carbon;
volatilizing the X component;
forming a graphene layer from the carbon;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
forming a gate abutting the gate dielectric; and
wherein depositing the XC carbide layer on a formation substrate comprises depositing amorphous tin carbide on a (0001) hexagonal boron nitride substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400° C., and wherein volatilizing the X component comprises sublimating tin by heating to a temperature of about 980° C.

### Claim 11

A method of forming a transistor comprising:
depositing a thermodynamically unstable XC carbide layer on a formation substrate;
decomposing the XC carbide layer into an X component and carbon;
volatilizing the X component;
forming a graphene layer from the carbon;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
forming a gate abutting the gate dielectric; and
wherein depositing the XC carbide layer on a formation substrate comprises depositing an epitaxial Ge0.95C0.05 layer on a (111) silicon carbide substrate.

### Claim 12 (depends on 11)

The method of claim 11, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400° C., wherein volatilizing the X component comprises sublimating germanium heated at a temperature of about 1080° C.

### Claim 13

A method of forming a transistor comprising:
depositing a thermodynamically unstable XC carbide layer on a formation substrate comprising depositing magnesium carbide on a (111) silicon carbide substrate;
decomposing the XC carbide layer into an X component and carbon;
volatilizing the X component;
forming a graphene layer from the carbon;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
forming a gate abutting the gate dielectric; and
wherein decomposing the XC carbide layer into an X component and carbon comprises heating the XC carbide layer to a temperature of about 400° C., wherein volatilizing the X component comprises heating to a temperature of about 600° C., and wherein forming the graphene layer comprises flash annealing at a temperature of about 850° C.

### Claim 14

A method of fabricating a transistor comprising:
providing a structural substrate comprising silicon;
forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer;
forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900° C. and forming the graphene layer by hydrocarbon chemical vapor deposition;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and
forming a gate abutting the gate dielectric.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.

### Claim 18 (depends on 14)

The method of claim 14, further including doping an impurity into the silicon carbide layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the impurity comprises iron or vanadium.

### Claim 20

A method of fabricating a transistor comprising:
providing a structural substrate comprising silicon;
forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer;
forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises:
annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900° C.;
treating with a hydrogen gas plasma at temperatures of about 100-400° C. to selectively remove surface silicon from a silicon carbide layer outer surface and produce a hydrogen terminated carbon rich surface; and
annealing at temperatures of about 850° C. or lower to desorb the hydrogen from the silicon carbide layer outer surface and form the graphene layer remaining carbon;
forming a source region abutting the graphene layer;
forming a drain region abutting the graphene layer;
forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and
forming a gate abutting the gate dielectric.

### Claim 21 (depends on 20)

The method of claim 20, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.

### Claim 22 (depends on 20)

The method of claim 20, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.

### Claim 23 (depends on 20)

The method of claim 20, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.

### Claim 24 (depends on 20)

The method of claim 20, further including doping an impurity into the silicon carbide layer.

### Claim 25 (depends on 24)

The method of claim 24, wherein the impurity comprises iron or vanadium.