# US 8,785,254 B2 · Method of manufacturing high-capacity semiconductor package

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- Number: US 8,785,254 B2
- Document ID: US8785254B2
- Status: Granted
- Kind: B2
- Application number: 13/846,492
- Filed: 2013-03-18
- Published: 2013-12-05
- Granted: 2014-07-22
- Earliest claimed: 2012-05-30
- Assignees: STS Semiconductor & Telecommunications Co., Ltd.
- Applicants: STS Semiconductor & Telecommunications Co., Ltd.
- Inventors: Jung Hwan Chun
- Web page: https://patentgrep.com/patent/US8785254B2

## CPC

- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a high-capacity semiconductor package includes preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape; attaching an interposer on a center area of the leadframe; stacking semiconductor chips stepwise on a first surface of the interposer; performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires; detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down; stacking semiconductor chips on a second surface of the interposer; performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires.

## Claims

### Claim 1

A method of manufacturing a stack-type high-capacity semiconductor package, the method comprising:
preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape;
attaching an interposer on a center area of the leadframe;
stacking a plurality of semiconductor chips stepwise on a first surface of the interposer;
performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer;
performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires;
detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down;
stacking a plurality of semiconductor chips on a second surface of the interposer;
performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and
performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires.

### Claim 2 (depends on 1)

The method of claim 1, wherein the tape is attached on the bottom surface of the leadframe.

### Claim 3 (depends on 1)

The method of claim 1, wherein tips of inner leads of the leadframe are in a state that enables wire bonding to be performed on both surfaces of the leadframe.

### Claim 4 (depends on 1)

The method of claim 1, wherein the interposer comprises one selected from a silicon wafer and a printed circuit board.

### Claim 5 (depends on 1)

The method of claim 1, wherein the number of semiconductor chips stacked is 2 to 8.

### Claim 6 (depends on 1)

The method of claim 1, wherein the semiconductor chips have polished bottom surfaces to decrease a thickness of the semiconductor chips.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first and second wire bonding processes comprise at least one selected from wire bonding that connects the semiconductor chips with each other, wire bonding that connects the semiconductor chip and the lead, wire bonding that connects the semiconductor chip and the interposer, and wire bonding that connects the interposer and the lead.

### Claim 8 (depends on 1)

The method of claim 1, after detaching the tape from the leadframe, further comprising performing a cleaning process on the bottom surface of the leadframe.

### Claim 9 (depends on 1)

The method of claim 1, after performing the second molding process, further comprising performing a marking process on a surface of a molded encapsulating material.

### Claim 10 (depends on 9)

The method of claim 9, after performing the marking process, further comprising a trimming process for separating a plurality of outer leads of the leadframe from one another; and a forming process for bending each of the plurality of outer leads.