# US 8,785,249 B2 · Three dimensional microelectronic components and fabrication methods for same

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- Number: US 8,785,249 B2
- Document ID: US8785249B2
- Status: Granted
- Kind: B2
- Application number: 13/488,804
- Filed: 2012-06-05
- Published: 2013-12-05
- Granted: 2014-07-22
- Earliest claimed: 2012-05-23
- Assignees: The Charles Stark Draper Laboratory, Inc.
- Applicants: Maurice Karpman
- Inventors: Maurice Karpman
- Web page: https://patentgrep.com/patent/US8785249B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H01F 17/0033: {with the coil helically wound around a magnetic core}
- H01F 41/046: {structurally combined with ferromagnetic material}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/66: Conductive materials thereof
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01923: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01933: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/01961: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951)}
- H10W 72/0198: {batch processes}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.

## Claims

### Claim 1

A method of forming an electrical component, the method comprising:
selecting a substrate;
forming a pattern of a first conductive material on a top surface of the substrate;
forming a pattern of a second conductive material on one of a bottom surface of the substrate and a dielectric layer formed over the pattern of the first conductive material;
dicing the substrate into a plurality of dies each having a first diced surface and a second diced surface, the first diced surface and the second diced surface formed by the dicing of the substrate;
securing the first diced surface of each of the plurality of dies to a retaining material;
encapsulating the plurality of dies in an encapsulent to form a reconstituted wafer; and
forming a pattern of a third conductive material on the second diced surfaces by metalizing a surface of the reconstituted wafer.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the first conductive material, the second conductive material, and the third conductive material comprise a metal.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the pattern of a first conductive material on the top surface of the substrate comprises forming a first plurality of metal lines on the top surface of the substrate.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the pattern of the second conductive material on the bottom surface of the substrate comprises forming a second plurality of metal lines on the bottom surface of the substrate.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the second plurality of metal lines on the bottom surface of the substrate comprises forming the second plurality of metal lines at positions horizontally displaced from the first plurality of metal lines on the top surface of the substrate.

### Claim 6 (depends on 5)

The method of claim 5, wherein selecting a substrate comprises selecting a substrate comprising a ferrite material.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a pattern of a fourth conductive material on the first diced surfaces.

### Claim 8 (depends on 7)

The method of claim 7, further comprising thinning the reconstituted wafer prior to one of forming the pattern of the third conductive material on the second diced surface and forming the pattern of the fourth conductive material on the first diced surface.

### Claim 9 (depends on 6)

The method of claim 6, wherein forming the pattern of the third conductive material on the second diced surface electrically connects a first metal line on the top side of the substrate to a second metal line on the bottom side of the substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the pattern of the fourth conductive material on the first diced surface electrically connects a fourth metal line on the top side of the substrate to the second metal line on the bottom side of the substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the electrical component formed comprises an inductor.

### Claim 12 (depends on 3)

The method of claim 3, wherein selecting a substrate comprises selecting a substrate comprising an insulating material.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming one or more bond pads in electrical communication with one or more of the first plurality of metal lines on a lower side of the reconstituted wafer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising thinning the reconstituted wafer prior to one of forming the one or more bond pads on the upper side of the reconstituted wafer and forming the one or more bond pads on the lower side of the reconstituted wafer.

### Claim 15 (depends on 12)

The method of claim 12, further comprising forming one or more bond pads in electrical communication with one or more of the first plurality of metal lines on an upper side of the reconstituted wafer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
incorporating the electrical component into an electronic module, one of the first plurality of metal lines configured as a through wafer via in the electronic module; and
electrically connecting a second electronic component in the electronic module to the one of the first plurality of metal lines.

### Claim 17 (depends on 15)

The method of claim 15, wherein the one or more of the first plurality of metal lines have a length in a direction normal to the first diced surface of greater than about 1 mm.

### Claim 18 (depends on 15)

The method of claim 15, wherein the one or more of the first plurality of metal lines have a length which is greater than about 15 times a thickness of the one or more of the first plurality of metal lines and about 15 times a width of the one or more of the first plurality of metal lines.

### Claim 19

A method of forming an electrical component, the method comprising:
forming a first pattern of metal lines on a top surface of a substrate, each of the metal lines in the first pattern having a length;
forming a second pattern of a metal lines one of a bottom surface of the substrate and a dielectric layer formed over the pattern of the first conductive material, the metal lines in the second pattern parallel to the metal lines in the first pattern;
dicing the substrate into one or more die having a first diced surface and a second diced surface formed by the dicing of the substrate; and
forming a third pattern of metal on the first diced surface;
wherein forming the second pattern of a metal lines comprises forming the second pattern of metal lines horizontally displaced from the metal lines in the first pattern in a direction normal to a direction defined by the length of a metal line in the first pattern of metal lines and in a plane parallel to the bottom surface of the substrate.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the third pattern of metal comprises forming a third pattern of metal lines.

### Claim 21 (depends on 20)

The method of claim 20, further comprising forming a fourth pattern of metal lines on the second diced surface.

### Claim 22 (depends on 21)

The method of claim 21, further comprising electrically connecting a metal line in the first pattern of metal lines and a metal line in the second pattern of metal lines with a metal line in one of the third pattern of metal lines and the fourth pattern of metal lines.

### Claim 23

A method of forming an electrical component, the method comprising:
selecting a substrate;
forming a layer of first sacrificial material on a top surface of the substrate;
forming a pattern of a first conductive material on a top surface of the layer of the first sacrificial material;
forming a layer of second sacrificial material on a top surface of the pattern of the first conductive material;
forming a pattern of a second conductive material on a top surface of the layer of the second sacrificial material;
forming an end structure physically joined to at least a portion of the pattern of the first conductive material and to at least a portion of the pattern of the second conductive material;
removing the substrate and the layer of the first sacrificial material from the pattern of the first conductive material;
embedding the pattern of the first conductive material and the pattern of the second conductive material in one of a reconstituted wafer and a multi-chip module; and
removing the end structure from the embedded pattern of the first conductive material and pattern of the second conductive material.

### Claim 24 (depends on 1)

The method of claim 1, wherein a plane defined by the first diced surface and a plane defined by the second diced surface are substantially perpendicular to a plane defined by the top surface and a plane defined by the bottom surface.