# US 8,785,248 B2 · Wafer level packaging using a lead-frame > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,248 B2 - Document ID: US8785248B2 - Status: Granted - Kind: B2 - Application number: 13/346,443 - Filed: 2012-01-09 - Published: 2013-04-11 - Granted: 2014-07-22 - Earliest claimed: 2011-10-10 - Assignees: Maxim Integrated Products, Inc. - Applicants: Ahmad R. Ashrafzadeh - Inventors: Ahmad R. Ashrafzadeh - Web page: https://patentgrep.com/patent/US8785248B2 ## CPC - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 90/811: {Multiple chips on leadframes} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/722: {between stacked chips} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed. ## Claims ### Claim 1 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer; c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer; etching the lead frame matrix to separate the lead frame contacts; d) dicing the first wafer. ### Claim 2 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer; c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer; attaching the lead frame matrix to a temporary substrate, etching the lead frame matrix to separate the lead frame contacts, then electrically connecting the lead frame contacts to the circuit contacts on the first wafer and removing the temporary substrate; d) dicing the first wafer. ### Claim 3 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer; c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer; coating the lead frame matrix with a polymer grinding the polymer to expose package contacts on the opposite side of the lead frame contacts before dicing; d) dicing the first wafer. ### Claim 4 (depends on 3) The method of claim 3 further comprising plating the package contacts with solder alloy before d). ### Claim 5 (depends on 3) The method of claim 3 wherein the lead frame matrix is etched part way through after b), at least part of the lead frame matrix that is not etched part way through forming at least one of the package contacts. ### Claim 6 (depends on 3) The method of claim 3 wherein the lead frame matrix is fabricated to have flexibility to accommodate the differential expansion between the lead frame matrix and the first wafer. ### Claim 7 (depends on 6) The method of claim 6 wherein electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer comprises soldering the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer, and wherein the lead frame matrix is restrained against expansion when being heated for soldering. ### Claim 8 (depends on 6) The method of claim 6 wherein the lead frame is fabricated so that the lead frame contacts are electrically separated by the dicing. ### Claim 9 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer; c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer; fabricating a second wafer having a matrix of second circuits thereon; thinning the second wafer; dicing the second wafer to form individual second circuits, each second circuit having an area that is less than the area of each first circuit; placing a second circuit on each of the first circuits and electrically connecting the first and second circuits; d) dicing the first wafer. ### Claim 10 (depends on 9) The method of claim 9 wherein the second circuits are placed on the first circuits and electrically connected to the first circuits before c). ### Claim 11 (depends on 9) The method of claim 9 wherein fabricating a lead frame matrix comprises fabricating a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer in areas not occupied by the second circuits. ### Claim 12 (depends on 11) The method of claim 11 wherein the first and second circuits are electrically connected by either reflow soldering or heat and pressure. ### Claim 13 (depends on 11) The method of claim 11 further comprising, after c), etching the lead frame matrix to separate the lead frame contacts. ### Claim 14 (depends on 11) The method of claim 11 wherein the lead frame matrix is etched part way through after b), at least part of the lead frame matrix that is not etched part way through forming at least one of the package contacts. ### Claim 15 (depends on 14) The method of claim 14 further comprising, after c), coating the lead frame matrix with a polymer, the polymer covering the part of the lead frame matrix that was etched part way through and not covering the package contacts. ### Claim 16 (depends on 15) The method of claim 15 further comprising plating the package contacts with solder alloy. ### Claim 17 (depends on 14) The method of claim 14 further comprising, after c), coating the lead frame matrix with a polymer and grinding the polymer to expose package contacts on the opposite side of the lead frame contacts before dicing. ### Claim 18 (depends on 17) The method of claim 17 further comprising plating the package contacts with solder alloy before d). ### Claim 19 (depends on 11) The method of claim 11 wherein the lead frame matrix is fabricated to have flexibility to accommodate the differential expansion between the lead frame matrix and the first wafer. ### Claim 20 (depends on 19) The method of claim 19 wherein electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer comprises soldering the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer, and wherein the lead frame matrix is restrained against expansion when being heated for soldering. ### Claim 21 (depends on 19) The method of claim 19 wherein the lead frame is fabricated so that the lead frame contacts are electrically separated by the dicing. ### Claim 22 (depends on 19) The method of claim 19 wherein the first and second circuits are electrically connected by either reflow soldering or heat and pressure. ### Claim 23 (depends on 22) The method of claim 22 wherein the lead frame matrix is etched part way through after b), at least part of the lead frame matrix that is not etched part way through forming at least one of the package contacts. ### Claim 24 (depends on 23) The method of claim 23 further comprising, after c), coating the lead frame matrix with a polymer, the polymer covering the part of the lead frame matrix that was etched part way through and not covering the package contacts. ### Claim 25 (depends on 24) The method of claim 24 further comprising plating the package contacts with solder alloy before d). ### Claim 26 (depends on 23) The method of claim 23 further comprising, after c), coating the lead frame matrix with a polymer. ### Claim 27 (depends on 26) The method of claim 26 further comprising plating the package contacts with solder alloy before d). ### Claim 28 (depends on 23) The method of claim 23 further comprising, after c), coating the lead frame matrix with a polymer and grinding the polymer to expose package contacts on the opposite side of the lead frame contacts before dicing. ### Claim 29 (depends on 9) The method of claim 9 wherein the first circuits are switching transistors for a switching regulator, and the second circuits are switching regulator controllers. ### Claim 30 A method of wafer level packaging comprising: fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof; fabricating a second wafer having a matrix of second circuits thereon; thinning the second wafer; dicing the second wafer to form individual second circuits, each second circuit having an area that is less than the area of each first circuit; placing a second circuit on each of the first circuits and electrically connecting the first and second circuits; fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer in areas not occupied by the second circuits; electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer; coating the first and second circuits with a polymer, the polymer not covering package contacts on the lead frame matrix on a side opposite the lead frame contacts; and dicing the first wafer and lead frame matrix. ### Claim 31 (depends on 30) The method of claim 30 further comprising attaching the lead frame matrix to a temporary substrate, etching the lead frame matrix to separate the lead frame contacts, then electrically connecting the lead frame contacts to the circuit contacts on the first wafer and removing the temporary substrate. ### Claim 32 (depends on 30) The method of claim 30 wherein the lead frame matrix is etched part way through before electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer, at least part of the lead frame matrix that is not etched part way through forming at least one of the package contacts. ### Claim 33 (depends on 32) The method of claim 32 further comprising plating the package contacts with solder alloy before dicing. ### Claim 34 (depends on 32) The method of claim 32 wherein, after electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer, etching the lead frame matrix to electrically separate leads of the lead frame. ### Claim 35 (depends on 30) The method of claim 30 wherein the lead frame matrix is fabricated to have flexibility to accommodate the differential expansion between the lead frame matrix and the first wafer. ### Claim 36 (depends on 35) The method of claim 35 wherein electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer comprises soldering the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer, and wherein the lead frame matrix is restrained against expansion when being heated for soldering. ### Claim 37 (depends on 35) The method of claim 35 wherein the lead frame is fabricated so that the lead frame contacts are electrically separated by the dicing.