# US 8,785,247 B2 · Chip package and method for forming the same

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- Number: US 8,785,247 B2
- Document ID: US8785247B2
- Status: Granted
- Kind: B2
- Application number: 13/893,015
- Filed: 2013-05-13
- Published: 2013-09-26
- Granted: 2014-07-22
- Earliest claimed: 2010-07-16
- Applicants: Xintec Inc.
- Inventors: Yu-Lung Huang; Yu-Ting Huang
- Web page: https://patentgrep.com/patent/US8785247B2

## CPC

- H10F 77/50: Encapsulations or containers (for photovoltaic modules H10F19/80)
- B81B 7/0077: {Other packages not provided for in groups B81B7/0035 - B81B7/0074}
- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/804: {Containers or encapsulations}
- H10W 72/0198: {batch processes}
- H10W 76/60: Seals
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

## Claims

### Claim 1

A method for forming a chip package, comprising:
providing a substrate having a first surface and a second surface, wherein a plurality of device regions are formed in the substrate, and the device regions are separated from each other by a plurality of predetermined scribe lines;
forming a passivation layer on the first surface of the substrate;
forming a polymer planar layer on the passivation layer;
patterning the polymer planar layer to form a plurality of patterned polymer planar layers, wherein the patterned polymer planar layers are located on a corresponding one of the device regions, respectively;
disposing a package substrate on the first surface of the substrate;
disposing a spacer layer between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a plurality of cavities on the substrate, and each of the patterned polymer planar layers does not extends to any one of the predetermined scribe lines, respectively; and
dicing the substrate and the package substrate along the predetermined scribe lines to form a plurality of separate chip packages.

### Claim 2 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the spacer layer comprises an inner portion and an outer portion, and the outer portion of the spacer layer directly contacts or covers a portion of the passivation layer.

### Claim 3 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the step of patterning the polymer planar layer comprises substantially and completely removing a portion of the polymer planar layer covering the predetermined scribe lines.

### Claim 4 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the step of dicing the substrate and the package substrate along the predetermined scribe lines comprises dicing the spacer layer.

### Claim 5 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the step of dicing the substrate and the package substrate along the predetermined scribe lines does not comprise dicing the patterned polymer planar layers.

### Claim 6 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein during the step of disposing the spacer layer, the spacer layer does not directly contact with the patterned polymer planar layers.

### Claim 7 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein during the step of disposing the spacer layer, the spacer layer directly contacts with the patterned polymer planar layers.

### Claim 8 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein each of the patterned polymer planar layers is completely located in a corresponding one of the cavities.

### Claim 9 (depends on 1)

The method for forming a chip package as claimed in claim 1, further comprising thinning the substrate from the second surface of the substrate.

### Claim 10 (depends on 9)

The method for forming a chip package as claimed in claim 9, further comprising:
after the substrate is thinned, removing a portion of the substrate to form a through-hole extending towards the first surface;
forming an insulating layer on a sidewall of the through-hole, wherein the insulating layer extends onto the second surface; and
forming a conducting layer on the insulating layer.

### Claim 11 (depends on 10)

The method for forming a chip package as claimed in claim 10, further comprising:
forming a patterned solder mask layer on the conducting layer such that a portion of the conducting layer is exposed; and
forming a conducting structure on the exposed conducting layer.

### Claim 12 (depends on 10)

The method for forming a chip package as claimed in claim 10, wherein one of the patterned polymer planar layers covers a portion of the through-hole.

### Claim 13 (depends on 10)

The method for forming a chip package as claimed in claim 10, wherein none of the patterned polymer planar layers covers a portion of the through-hole.

### Claim 14 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the spacer layer comprises an inner portion and an outer portion, and the outer portion of the spacer layer is thicker than the inner portion of the spacer layer.

### Claim 15 (depends on 1)

The method for forming a chip package as claimed in claim 1, further comprising disposing at least an optical element in each of the cavities and on each of the device regions.

### Claim 16 (depends on 15)

The method for forming a chip package as claimed in claim 15, wherein the optical element comprises a light filter layer, a lens, or combinations thereof.

### Claim 17 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the package substrate comprises a transparent substrate.

### Claim 18 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein an outer sidewall of one of the separate chip packages comprises the diced package substrate, the spacer layer, the passivation layer, and the substrate.

### Claim 19 (depends on 18)

The method for forming a chip package as claimed in claim 18, wherein the outer sidewall of one of the separate chip packages does not comprise the patterned polymer planar layers.

### Claim 20 (depends on 1)

The method for forming a chip package as claimed in claim 1, wherein the device regions comprise image sensor devices.