# US 8,785,245 B2 · Method of manufacturing stack type semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,245 B2 - Document ID: US8785245B2 - Status: Granted - Kind: B2 - Application number: 13/167,324 - Filed: 2011-06-23 - Published: 2012-01-19 - Granted: 2014-07-22 - Earliest claimed: 2010-07-15 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Woo-jae Kim - Inventors: Woo-jae Kim - Web page: https://patentgrep.com/patent/US8785245B2 ## CPC - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/016: {using moulds} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 72/50: Bond wires - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a stack type semiconductor package is provided. A lower semiconductor package including a circuit board on which a semiconductor chip and electrode pads are formed is provided. A plurality of metal pins are adhered and fixed to the electrode pads of the circuit board of the lower semiconductor package, respectively. An upper semiconductor package is vertically stacked on the lower semiconductor package via the metal pins. ## Claims ### Claim 1 A method of manufacturing a stack type semiconductor package, comprising: providing a lower semiconductor package comprising a circuit board on which a semiconductor chip and electrode pads are formed; fixing a plurality of metal pins respectively to the electrode pads of the circuit board of the lower semiconductor package by using a jig comprising a metal plate comprising an upper surface, a lower surface, and a plurality of holes formed in the metal plate, wherein the plurality of holes are positioned to correspond to a same arrangement by which the electrode pads of the circuit board are positioned, positioning the metal pins in the holes with the metal pins protruding from the upper surface of the metal plate, stacking the jig including the metal pins on the circuit board, and separating the metal plate from the metal pins and the circuit board, wherein the protruding metal pins pass through the upper and lower surfaces of the metal plate as the jig is separated, and wherein the plurality of metal pins comprise a plating layer formed at a lower portion of the metal pins, the plating layer being formed prior to fixing the plurality of metal pins; and vertically stacking an upper semiconductor package on the lower semiconductor package via the metal pins. ### Claim 2 (depends on 1) The method of claim 1, wherein the metal pins extend vertically with respect to the circuit board. ### Claim 3 (depends on 1) The method of claim 1, wherein the metal pins extend to a height which is higher than that of the semiconductor chip of the lower semiconductor package. ### Claim 4 (depends on 1) The method of claim 1, wherein ends of the metal pins connected to the upper semiconductor package are formed flat. ### Claim 5 (depends on 4) The method of claim 4, wherein holes are formed in centers of the ends of the metal pins which are connected to the upper semiconductor package. ### Claim 6 (depends on 1) The method of claim 1, wherein an organic solderability preservative (OSP) surface treatment is performed on ends of the metal pins which are connected to the upper semiconductor package. ### Claim 7 (depends on 1) The method of claim 1, wherein the semiconductor chip is electrically connected to the circuit board by using one of a flip-chip method and a wire bonding method. ### Claim 8 (depends on 1) The method of claim 1, wherein after fixing the metal pins, further comprising forming a sealing layer which leaves exposed upper surfaces of the metal pins and covers the circuit board, the semiconductor chip, and remaining portions of the metal pins. ### Claim 9 A method of manufacturing a stack type semiconductor package, comprising: providing a lower semiconductor package comprising a circuit board comprising an upper surface to which a semiconductor chip is adhered and on which a plurality of electrode pads are positioned; fixing a plurality of metal pins to the circuit board using a jig comprising a metal plate and a plurality of holes formed in the metal plate, wherein the holes are positioned to correspond to a same arrangement by which the electrode pads of the circuit board are positioned, positioning the metal pins in the holes, stacking the jig including the meal pins on the circuit board, wherein the metal pins are positioned on the circuit board to correspond to the same arrangement by which the electrode pads are positioned, and wherein the metal plate comprises an upper surface and a lower surface, the lower surface faces the upper surface of the lower semiconductor package and the metal pins protrude from the upper surface of the metal plate, and separating the metal plate from the metal pins and the circuit board; and vertically stacking an upper semiconductor package on the metal pins, such that the upper surface of the lower semiconductor package and the lower surface of the metal plate are adjacent to each other, wherein the upper semiconductor package is electrically connected to the metal pins. ### Claim 10 (depends on 9) The method of claim 9, wherein the upper semiconductor package comprises upper electrode pads and external connection terminals, wherein the upper electrode pads correspond to the metal pins and are connected to the metal pins through the external connection terminals. ### Claim 11 (depends on 10) The method of claim 10, wherein pitches of the metal pins are equal to pitches of the external connection terminals. ### Claim 12 (depends on 9) The method of claim 9, wherein the metal pins comprise copper layers. ### Claim 13 (depends on 9) The method of claim 9, wherein the semiconductor chip is formed on the upper surface of the circuit board using a flip-chip method, wherein an underfill layer is formed on the circuit board under the semiconductor chip. ### Claim 14 (depends on 9) The method of claim 9, wherein the upper semiconductor package is a multi-chip package. ### Claim 15 A method of manufacturing a stack type semiconductor package, comprising: providing a lower semiconductor package comprising a circuit board comprising an upper surface to which a semiconductor chip is adhered and on which a plurality of electrode pads are positioned; forming conductive adhesive layers respectively on the electrode pads of the circuit board; providing a jig comprising a metal plate and holes formed in the metal plate, wherein the holes are positioned to correspond to the same arrangement by which the electrode pads of the circuit board are positioned, and wherein the metal plate comprises an upper surface and a lower surface, the lower surface faces the upper surface of the lower semiconductor package; positioning metal pins in the holes, wherein the metal pins protrude from the upper surface of the metal plate; stacking the jig comprising the metal pins on the conductive adhesive layers, wherein the metal pins are positioned to correspond to the same arrangement by which the electrode pads are positioned, such that the upper surface of the lower semiconductor package and the lower surface of the metal plate are adjacent to each other; reflowing the conductive adhesive layers; separating the metal plate of the jig from the circuit board to form the metal pins on the circuit board, wherein the metal pins are positioned to correspond to the same arrangement by which the electrode pads are positioned, and wherein the protruded metal pins pass through the upper and lower surfaces of the metal plate as the jig is separated; and vertically stacking an upper semiconductor package on the metal pins, wherein the upper semiconductor package is electrically connected to the metal pins. ### Claim 16 (depends on 15) The method of claim 15, wherein when reflowing the conductive adhesive layers, the metal pins are adhered to the conductive adhesive layers, respectively. ### Claim 17 (depends on 15) The method of claim 15, wherein the upper semiconductor package comprises external connection terminals, wherein pitches of the metal pins are equal to pitches of the external connection terminals. ### Claim 18 A method of manufacturing a stack type semiconductor package, comprising: providing a lower semiconductor package comprising a circuit board having an upper surface on which a plurality of electrode pads are positioned; providing a jig comprising a metal plate and holes formed in the metal plate, wherein the holes are spaced apart from each other at a predetermined pitch, and wherein the metal plate comprises an upper surface and a lower surface, the lower surface faces the upper surface of the lower semiconductor package and metal pins protrude from the upper surface of the metal plate; positioning the metal pins in the holes; stacking the jig comprising the metal pins on the circuit board, such that the upper surface of the lower semiconductor package and the lower surface of the metal plate are adjacent to each other; separating the metal plate of the jig from the circuit hoard to form the metal pins on the circuit board, wherein the protruded metal pins pass through the upper and lower surfaces of the metal plate as the jig is separated, and wherein the metal pins are spaced apart from each other at the predetermined pitch; and vertically stacking an upper semiconductor package on the metal pins, wherein the upper semiconductor package is electrically connected to the metal pins via a plurality of connection terminals spaced apart from each other at the predetermined pitch.