# US 8,785,244 B2 · Wafer level packaging using a lead-frame > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,244 B2 - Document ID: US8785244B2 - Status: Granted - Kind: B2 - Application number: 13/689,416 - Filed: 2012-11-29 - Published: 2013-04-11 - Granted: 2014-07-22 - Earliest claimed: 2011-10-10 - Assignees: Maxim Integrated Products, Inc. - Applicants: Ahmad R. Ashrafzadeh - Inventors: Ahmad R. Ashrafzadeh - Web page: https://patentgrep.com/patent/US8785244B2 ## CPC - H10W 74/01: Manufacture or treatment - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 72/0198: {batch processes} - H10W 74/014: {using batch processing} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 72/072: {of bump connectors} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07236: {Soldering or alloying} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/722: {between stacked chips} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed. ## Claims ### Claim 1 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts formed by a plurality of redistribution layers accessible from a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer, each lead frame including a plurality of lead frame portions extending toward each other from opposite sides of the lead frame, the lead frame portions extending less than half way across the lead frame so that tips of lead frame portions from one side of the lead frame do not extend between tips of the lead frame portions from the other side of the lead frame; c) electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer; etching the lead frame matrix to separate the lead frame portions; d) dicing the first wafer. ### Claim 2 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts formed by a plurality of redistribution layers accessible from a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer, each lead frame including a plurality of lead frame portions extending toward each other from opposite sides of the lead frame, the lead frame portions extending less than half way across the lead frame so that tips of lead frame portions from one side of the lead frame do not extend between tips of the lead frame portions from the other side of the lead frame; attaching the lead frame matrix to a temporary substrate, etching the lead frame matrix to separate the lead frame portions electrically connecting the lead frame portions to the circuit contacts on the first wafer and removing the temporary substrate; d) dicing the first wafer. ### Claim 3 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts formed by a plurality of redistribution layers accessible from a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer, each lead frame including a plurality of lead frame portions extending toward each other from opposite sides of the lead frame, the lead frame portions extending less than half way across the lead frame so that tips of lead frame portions from one side of the lead frame do not extend between tips of the lead frame portions from the other side of the lead frame; c) electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer; coating the lead frame matrix with a polymer; grinding the exposed surface of the polymer to expose package contacts on the opposite side of the lead frame portions; d) dicing the first wafer. ### Claim 4 (depends on 3) The method of claim 3 further comprising plating the package contacts with solder alloy before d). ### Claim 5 (depends on 3) The method of claim 3 wherein the lead frame matrix is fabricated to have flexibility to accommodate the differential expansion between the lead frame matrix and the first wafer. ### Claim 6 (depends on 5) The method of claim 5 wherein electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer comprises soldering the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer, and wherein the lead frame matrix is restrained against expansion when being heated for soldering. ### Claim 7 (depends on 5) The method of claim 5 wherein the lead frame is fabricated so that the lead frame portions are electrically separated by the dicing. ### Claim 8 A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts formed by a plurality of redistribution layers accessible from a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer, each lead frame including a plurality of lead frame portions extending toward each other from opposite sides of the lead frame, the lead frame portions extending less than half way across the lead frame so that tips of lead frame portions from one side of the lead frame do not extend between tips of the lead frame portions from the other side of the lead frame; c) electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer; fabricating a second wafer having a matrix of second circuits thereon; thinning the second wafer; dicing the second wafer to form individual second circuits, each second circuit having an area that is less than the area of each first circuit; placing a second circuit on each of the first circuits and electrically connecting the first and second circuits; d) dicing the first wafer. ### Claim 9 (depends on 8) The method of claim 8 wherein the second circuits are placed on the first circuits and electrically connected to the first circuits before c). ### Claim 10 (depends on 8) The method of claim 8 wherein fabricating a lead frame matrix comprises fabricating a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer in areas not occupied by the second circuits. ### Claim 11 (depends on 10) The method of claim 10 wherein the first and second circuits are electrically connected by either reflow soldering or heat and pressure. ### Claim 12 (depends on 10) The method of claim 10 further comprising, after c), etching the lead frame matrix to separate the lead frame portions. ### Claim 13 (depends on 10) The method of claim 10 wherein the lead frame matrix is fabricated to have flexibility to accommodate the differential expansion between the lead frame matrix and the first wafer. ### Claim 14 (depends on 13) The method of claim 13 wherein electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer comprises soldering the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer, and wherein the lead frame matrix is restrained against expansion when being heated for soldering. ### Claim 15 (depends on 13) The method of claim 13 wherein the lead frame is fabricated so that the lead frame portions are electrically separated by the dicing. ### Claim 16 (depends on 13) The method of claim 13 wherein the first and second circuits are electrically connected by either reflow soldering or heat and pressure. ### Claim 17 (depends on 8) The method of claim 8 wherein the first circuits are switching transistors for a switching regulator, and the second circuits are switching regulator controllers. ### Claim 18 A method of wafer level packaging comprising: fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof; fabricating a second wafer having a matrix of second circuits thereon; thinning the second wafer; dicing the second wafer to form individual second circuits, each second circuit having an area that is less than the area of each first circuit; placing a second circuit on each of the first circuits and electrically connecting the first and second circuits; fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer in areas not occupied by the second circuits, each lead frame including a plurality of lead frame portions extending toward each other from opposite sides of the lead frame, the lead frame portions extending less than half way across the lead frame so that tips of lead frame portions from one side of the lead frame do not extend between tips of the lead frame portions from the other side of the lead frame; electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer; coating the first and second circuits with a polymer, the polymer not covering package contacts on the lead frame matrix; and dicing the first wafer and lead frame matrix. ### Claim 19 (depends on 18) The method of claim 18 further comprising attaching the lead frame matrix to a temporary substrate, etching the lead frame matrix to separate the lead frame portions, then electrically connecting the lead frame portions to the circuit contacts on the first wafer and removing the temporary substrate. ### Claim 20 (depends on 18) The method of claim 18 wherein at least part of the lead frame matrix forms at least one of the package contacts. ### Claim 21 (depends on 20) The method of claim 20 further comprising plating the package contacts with solder alloy before dicing. ### Claim 22 (depends on 20) The method of claim 20 wherein, after electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer, etching the lead frame matrix to electrically separate leads of the lead frame. ### Claim 23 (depends on 18) The method of claim 18 wherein the lead frame matrix is fabricated to have flexibility to accommodate the differential expansion between the lead frame matrix and the first wafer. ### Claim 24 (depends on 23) The method of claim 23 wherein electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer comprises soldering the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer, and wherein the lead frame matrix is restrained against expansion when being heated for soldering. ### Claim 25 (depends on 23) The method of claim 23 wherein the lead frame is fabricated so that the lead frame portions are electrically separated by the dicing.