# US 8,785,243 B2 · Method for manufacturing a thin film transistor array panel

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- Number: US 8,785,243 B2
- Document ID: US8785243B2
- Status: Granted
- Kind: B2
- Application number: 13/567,823
- Filed: 2012-08-06
- Published: 2013-10-03
- Granted: 2014-07-22
- Earliest claimed: 2012-04-02
- Assignees: Samsung Display Co., Ltd.; Industry-Academic Cooperation Foundation, Dankook University
- Applicants: Byung Du Ahn; Jun Hyung Lim; Jin Seong Park
- Inventors: Byung Du Ahn; Jun Hyung Lim; Jin Seong Park
- Web page: https://patentgrep.com/patent/US8785243B2

## CPC

- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/20: of semiconductor materials
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes, forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate, first heat treating the substrate comprising the oxide semiconductor layer, forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes facing each other, and forming a passivation layer on the source electrode and the drain electrode. The first heat treating is performed at more than 1 atmosphere and at most 50 or less atmospheres.

## Claims

### Claim 1

A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate;
performing a first heat treatment on the substrate comprising the oxide semiconductor layer, at a pressure in the range of more than 1 atmosphere to 50 atmospheres;
forming a source electrode and a drain electrode on the oxide semiconductor layer, after performing the first heat treatment; and
forming a passivation layer on the source electrode and the drain electrode,
wherein the first heat treatment does not change a crystalline structure of the oxide semiconductor layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first heat treatment is performed at a temperature of at most 400° C.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a pixel electrode on the passivation layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the oxide semiconductor comprises one of tantalum-indium-zinc oxide, indium-zinc-tin oxide, and indium-gallium-zinc oxide.

### Claim 5 (depends on 2)

The method of claim 2, wherein the first heat treatment is performed for at least 30 minutes.

### Claim 6 (depends on 5)

The method of claim 5, further comprising performing a second heat treatment after forming the passivation layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second heat treatment is performed at a temperature of 400° C. or less.

### Claim 8 (depends on 7)

The method of claim 7, wherein the second heat treatment is performed at 1 atmosphere.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first heat treatment is performed at a pressure in the range of 5 atmospheres to 30 atmospheres.

### Claim 10 (depends on 3)

The method of claim 3, further comprising performing a heat treatment on the substrate comprising the pixel electrode.

### Claim 11

A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate;
forming an etch stopper on the oxide semiconductor layer;
performing a first heat treatment on the substrate comprising the etch stopper, at a pressure in the range of more than 1 atmosphere to 50 atmospheres;
forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes contacting opposing portions of the etch stopper; and
forming a passivation layer on the substrate comprising the source electrode and the drain electrode.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first heat treatment is performed at a temperature of 400° C. or less.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first heat treatment is performed for at least 30 minutes.

### Claim 14 (depends on 13)

The method of claim 13, further comprising performing a second heat treatment on the substrate comprising the passivation layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second heat treatment is performed at a temperature of 400° C. or less.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second heat treatment is performed at 1 atmosphere.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first heat treatment is performed at a pressure in the range of 5 atmospheres to 30 atmospheres.