Generating interface adjustment signals in a device-to-device interconnection system
AssigneeRambus Inc.
InventorStephen G. Tell
Life of this patent
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Abstract
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Claims16
A circuit comprising:
- a processor to implement control of interface operations;
- a bus coupled to said processor;
- and
- a plurality of interface control circuits coupled to said bus, a respective interface control circuit comprising a respective processing element;
- wherein a respective interface control circuit is configured to receive one or more respective signals from one or more respective devices external to the circuit;
- wherein the respective interface control circuit is further configured to process the one or more respective received signals to generate one or more respective interface adjustment signals based on the results of operations performed by at least one of the respective processing element and said processor, said operations using information derived from the one or more respective received signals;
- and
- wherein the interface control circuits are operable in a first mode to generate one or more interface adjustment signals based on the results of operations performed by the processing elements in response to one or more opcodes transmitted by the processor.
A method for generating interface adjustment signals, performed at a circuit with a processor, a bus coupled to the processor, and a plurality of interface control circuits coupled to the bus, a respective interface control circuit comprising a respective processing element, the method comprising:
- receiving, at a respective interface control circuit, one or more respective signals from one or more respective devices external to the circuit;
- processing, at the respective interface control circuit, the one or more respective received signals to generate one or more respective interface adjustment signals based on results of operations performed by at least one of the respective processing element and the processor, said operations using information derived from the one or more respective received signals;
- operating the circuit in a first mode, wherein operating the circuit in the first mode includes generating, at the respective interface control circuit, one or more interface adjustment signals based on the results of operations performed by said processing elements of said plurality of interface control circuits in response to one or more opcodes transmitted by said processor.
Dependencies are inferred from the claim text.