US 8,782,321 B2Granted

PCI express tunneling over a multi-protocol I/O interconnect

AssigneeIntel Corporation

InventorsDavid J. Harriman, Maxim Dan

Life of this patent

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Abstract

Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

Claims19

Dependent claims

A method comprising:

establishing, by a multiprotocol input-output (I/O) interconnect of a computer apparatus, a first communication path between ports of a switching fabric of the multi-protocol I/O interconnect in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, the first communication path communicatively connecting the PCIe device to the computer apparatus;
establishing, by the multiprotocol input-output I/O interconnect, a second communication path between the switching fabric and a PCIe controller;
and
routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths wherein-establishing a first communication path includes establishing, by the multiprotocol input-output I/O interconnect, a virtual PCIe link between at least two adapters implemented by the ports of the switching fabric, in response to the PCIe protocol packets having a packet header that includes a protocol defined field specifying maintenance of synchronization between the adapters of the ports of the switching fabric.

1 more element

A computer-readable non-transitory storage medium;

and
a plurality of programming instructions stored in the storage medium, and configured to cause an apparatus, in response to execution of the programming instructions by the apparatus, to:
establish a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, the first communication path communicatively connecting the PCIe device to the computer apparatus;
establish a second communication path between the switching fabric and a PCIe controller;
and
route, by the multi-protocol I/O interconnect, PCIe protocol packets of a protocol of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths, wherein to establish a first communication path includes to establish a virtual PCIe link between at least two adapters implemented by the ports of the switching fabric, in response to the PCIe protocol packets having a packet header that includes a protocol defined field specifying maintenance of synchronization between the adapters of the ports of the switching fabric.

3 more elements

A system comprising:

an I/O complex including a multi-protocol I/O interconnect having a switching fabric comprising a plurality of switches;
one or more processors operatively coupled with the I/O complex;
a non-transitory computer-readable storage medium operatively coupled with the one or more processors, and having stored therein a plurality of programming instructions configured to enable the system, in response to execution of the programming instructions, to:
establish a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, the first communication path communicatively connecting the PCIe device to the computer apparatus;
establish a second communication path between the switching fabric and a PCIe controller;
and
route, by the multi-protocol I/O interconnect, PCIe protocol packets of a protocol of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths, wherein to establish a first communication path includes to establish a virtual PCIe link between at least two adapters implemented by the ports of the switching fabric, in response to the PCIe protocol packets having a packet header that includes a protocol defined field specifying maintenance of synchronization between the adapters of the ports of the switching fabric;
and
a display device operatively coupled to the I/O complex and the one or more processors.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/369,140Filed 8 Feb 2012
Published: US 2013/0205053 A18 Aug 2013
Granted: 15 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 13/4022
Coupling between buses: using switching circuits, e.g. switching matrix, connection or expansion network
G06F 13/387
Using universal interface adapter: for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters…
G06F 13/4295
On a serial bus, e.g. I2C bus, SPI bus: using an embedded synchronisation
G06F 2213/0026
Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central…:…