Nonvolatile semiconductor memory

A nonvolatile semiconductor memory comprising:

• a semiconductor substrate;
• first to n-th (n is a natural number not less than 2) semiconductor layers which are stacked in order from the semiconductor substrate side in a first direction perpendicular to a surface of the semiconductor substrate and extend in a second direction parallel to the surface of the semiconductor substrate, and the semiconductor layers isolated each other and having a stair case pattern in a first end of the first to n-th semiconductor layers in the second direction;
• a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the first to n-th semiconductor layers, the common semiconductor layer having an upper surface higher than an upper surface of the n-th semiconductor layer;
• a first electrode connected to the common semiconductor layer;
• a second electrode connected to the first to n-th semiconductor layers in a second end of the first to n-th semiconductor layers in the second direction;
• first to n-th memory strings which are provided in corresponding to the first to n-th semiconductor layers, channels of the first to n-th memory strings being provided in the first to n-th semiconductor layers respectively;
• first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and select one of the first to n-th memory strings;
• and
• first to n-th impurity regions which are provided in the first to n-th semiconductor layers adjacent to the common semiconductor layer respectively,
• wherein the i-th layer select transistor (i is one of 1 to n) comprises first to n-th sub transistors which are provided in order from the first semiconductor layer between the first semiconductor layer and the upper surface of the common semiconductor layer,
• the i-th sub transistor of the i-th layer select transistor comprises the i-th impurity region as a channel which is provided in the i-th semiconductor layer, and
• the i-th impurity region has an impurity concentration higher than an impurity concentration of a channel of the sub transistor except the i-th sub transistor among the first to n-th sub transistors of the i-th layer select transistor.