# US 8,772,924 B2 · Forming in-situ micro-feature structures with coreless packages

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- Number: US 8,772,924 B2
- Document ID: US8772924B2
- Status: Granted
- Kind: B2
- Application number: 13/852,277
- Filed: 2013-03-28
- Published: 2013-08-22
- Granted: 2014-07-08
- Earliest claimed: 2010-04-06
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ravi Nalla; Mathew J. Manusharow
- Web page: https://patentgrep.com/patent/US8772924B2

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 40/10: Arrangements for heating
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H05K 1/0209: {External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings}
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/00: Package configurations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

## Claims

### Claim 1

A structure comprising:
a die disposed in a package structure;
a dielectric material adjacent the die;
die pad interconnect structures in the die area; and
at least one micro-feature structure disposed on a top portion of the die, wherein the at least one micro-feature structure is disposed directly on an etch stop material disposed directly on the die.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the at least one micro-feature structure comprises a copper material.

### Claim 3 (depends on 1)

The structure of claim 1 wherein the package structure comprises a portion of a coreless bumpless buildup package structure.

### Claim 4 (depends on 1)

The structure of claim 1 wherein the at least one micro-feature structure comprises a heat spreader.

### Claim 5 (depends on 2)

The structure of claim 2 wherein the die is partially embedded into the coreless substrate, and wherein the dielectric material is formed along a portion of a sidewall of the die and not on a top portion of the die.

### Claim 6 (depends on 5)

The structure of claim 5 wherein the etch stop material comprises nickel.

### Claim 7 (depends on 3)

The structure of claim 3 wherein the package structure further comprises at least one of a PoP land structure and an inductor structure on a top surface of the package structure, wherein the at least one micro-channel structure and the at least one PoP land structure and inductor structure comprise the same material.