# US 8,772,921 B2 · Interposer for semiconductor package

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- Number: US 8,772,921 B2
- Document ID: US8772921B2
- Status: Granted
- Kind: B2
- Application number: 13/347,683
- Filed: 2012-01-10
- Published: 2012-05-03
- Granted: 2014-07-08
- Earliest claimed: 2008-10-23
- Assignees: United Test and Assembly Center Ltd.
- Applicants: Chin Hock Toh; Yao Huang Huang; Ravi Kanth Kolan; Wei Liang Yuan; Susanto Tanary; Yi Sheng Anthony Sun
- Inventors: Chin Hock Toh; Yao Huang Huang; Ravi Kanth Kolan; Wei Liang Yuan; Susanto Tanary; Yi Sheng Anthony Sun
- Web page: https://patentgrep.com/patent/US8772921B2

## CPC

- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H05K 3/3478: Application of solder preforms; Transferring prefabricated solder patterns
- H05K 2201/09481: Via in pad; Pad over filled via
- H05K 2201/09509: Blind vias, i.e. vias having one side closed
- H05K 2201/09572: Solder filled plated through-hole in the final product
- H05K 2201/10378: Interposers
- H05K 2203/043: Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49155: Manufacturing circuit on or in base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

## Claims

### Claim 1

A device package comprising:
an interposer which includes an interposer base having first and second surfaces;
a redistribution layer disposed on a first surface of the interposer base;
interposer pads coupled to the redistribution layer;
interposer vias through the interposer base in communication with the redistribution layer;
interposer contacts coupled to the interposer pads via the redistribution layer, wherein an interposer contact includes a via portion disposed in the interposer via and a surface portion on the second surface of the interposer base, wherein the via portion and surface portion comprise a single material, and the interposer contact is a single unitary contact of which no seam or interface exist between the via portion and the surface portion;
a die comprising die contacts, the die contacts coupled to the interposer pads; and
a package substrate having package pads on a first surface, wherein the interposer contacts are coupled to the package pads.

### Claim 2 (depends on 1)

The device package of claim 1 wherein the single material comprises a reflowable conductive material.

### Claim 3 (depends on 1)

The device package of claim 1 wherein the reflowable material comprises solder.

### Claim 4 (depends on 1)

The device package of claim 1 wherein the base comprises a material having a coefficient of thermal expansion at least similar to that of the die.

### Claim 5 (depends on 1)

The device package of claim 1 wherein the base comprises silicon.

### Claim 6 (depends on 1)

The device package of claim 1 wherein the die comprises a flip chip.

### Claim 7 (depends on 1)

The device package of claim 1 wherein a die stack comprising a plurality of dies serving as active interposers are coupled to the interposer.

### Claim 8 (depends on 1)

The device package of claim 1 further comprises a cap encapsulating the die, interposer and the first surface of the package substrate.

### Claim 9

A device package comprising:
an interposer base having first and second surfaces;
a redistribution layer disposed on a first surface of the interposer base;
at least one interposer pad disposed over and coupled to the redistribution layer;
at least one interposer via through the interposer base in communication with the redistribution layer;
an integrated interposer contact coupled to the interposer pad via the redistribution layer, the integrated interposer contact having a via portion disposed in the interposer via and a surface portion on the second surface of the interposer base, wherein the via portion comprises reflowable conductive material of the surface portion;
a die comprising at least one die contact, the die contact is coupled to the interposer pad; and
a package substrate having at least one package pad on a first surface, wherein the interposer contact are coupled to the package pad.

### Claim 10 (depends on 9)

The device package of claim 9 wherein the reflowable conductive material comprises solder.

### Claim 11 (depends on 9)

The device package of claim 9 wherein the base comprises a material having a coefficient of thermal expansion (CTE) at least similar to that of the die.

### Claim 12 (depends on 9)

The device package of claim 9 wherein the interposer base comprises silicon.

### Claim 13 (depends on 9)

The device package of claim 9 comprises a first insulating layer disposed between the first surface of the interposer base and the redistribution layer.

### Claim 14 (depends on 13)

The device package of claim 13 comprises a second insulating layer lining sidewalls of the via and on the second surface of the interposer base.

### Claim 15 (depends on 9)

The device package of claim 9 wherein a die stack comprising a plurality of dies serving as active interposers are coupled to the interposer.

### Claim 16 (depends on 9)

The device package of claim 9 further comprises a cap encapsulating the die, interposer and the first surface of the package substrate.

### Claim 17 (depends on 9)

The device package of claim 9 wherein the die comprises a flip chip.

### Claim 18 (depends on 9)

The device package of claim 9 wherein the die comprises a die cap which encapsulates the die and top surface of the interposer.

### Claim 19 (depends on 1)

The device package of claim 1 wherein the die comprises a die cap which encapsulates the die and a top surface of the interposer.

### Claim 20 (depends on 1)

The device package of claim 1 wherein the interposer comprises an inactive interposer.