# US 8,772,920 B2 · Interconnection and assembly of three-dimensional chip packages

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- Number: US 8,772,920 B2
- Document ID: US8772920B2
- Status: Granted
- Kind: B2
- Application number: 13/182,220
- Filed: 2011-07-13
- Published: 2013-01-17
- Granted: 2014-07-08
- Earliest claimed: 2011-07-13
- Assignees: Oracle International Corporation
- Applicants: Hiren D. Thacker; John E. Cunningham; Ivan Shubin; Ashok V. Krishnamoorthy
- Inventors: Hiren D. Thacker; John E. Cunningham; Ivan Shubin; Ashok V. Krishnamoorthy
- Web page: https://patentgrep.com/patent/US8772920B2

## CPC

- H10W 90/00: Package configurations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/07231: {Techniques}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07554: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 90/20: Configurations of stacked chips
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

## Claims

### Claim 1

A chip package, comprising:
a group of semiconductor dies arranged in a plank stack in an x direction, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces;
positive features mechanically coupled to the negative features on adjacent semiconductor dies, thereby aligning the semiconductor dies in the plank stack; and
an interposer plate electrically coupled to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction;
wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.

### Claim 2 (depends on 1)

The chip package of claim 1, wherein a first electrical pad on a given semiconductor die is included in a second negative feature recessed below one of the surfaces of the given semiconductor die.

### Claim 3 (depends on 2)

The chip package of claim 2, wherein the second negative feature is included in a dicing lane of the given semiconductor die.

### Claim 4 (depends on 1)

The chip package of claim 1, wherein the intervening conductive material includes solder balls.

### Claim 5 (depends on 4)

The chip package of claim 4, wherein the edges of the semiconductor dies are surrounded by the solder balls.

### Claim 6 (depends on 1)

The chip package of claim 1, wherein the intervening conductive material includes mechanically compliant electrical connectors.

### Claim 7 (depends on 6)

The chip package of claim 6, wherein the mechanically compliant electrical connectors include an array of spring connectors.

### Claim 8 (depends on 7)

The chip package of claim 7, wherein surfaces of a given semiconductor die are positioned between and mechanically coupled to at least a pair of spring connectors in the array of spring connectors.

### Claim 9 (depends on 1)

The chip package of claim 1, wherein a first electrical pad on a given semiconductor die is electrically coupled to an additional pad on the given semiconductor die by an electrical signal line.

### Claim 10 (depends on 1)

The chip package of claim 1, further comprising:
a mechanical-alignment plate; and
mechanical-alignment components, wherein the plank stack is mechanically coupled to the mechanical-alignment plate by the mechanical-alignment components, thereby facilitating alignment of the semiconductor dies in the plank stack; and
wherein the mechanical-alignment plate is mechanically coupled to the plank stack on an opposite face of the plank stack from the interposer plate.

### Claim 11 (depends on 10)

The chip package of claim 10, wherein the mechanical-alignment components include at least one of: spheres, clamps and pins.

### Claim 12 (depends on 1)

The chip package of claim 1, wherein the semiconductor dies include third electrical pads proximate to the edges of the semiconductor dies along the y direction;
wherein the interposer plate is further electrically coupled to the semiconductor dies along the y direction; and
wherein the electrical coupling to the semiconductor dies is between the third electrical pads, fourth electrical pads proximate to the surface of the interposer plate along the y direction, and the intervening conductive material between the third electrical pads and the fourth electrical pads.

### Claim 13 (depends on 1)

The chip package of claim 1, wherein the second electrical pads include one of: discrete pads and a continuous electrical signal line on the interposer plate.

### Claim 14 (depends on 1)

The chip package of claim 1, further comprising mechanical-alignment components mechanically coupled to the edges of the semiconductor dies and the interposer plate.

### Claim 15 (depends on 1)

The chip package of claim 1, wherein the semiconductor dies are mechanically coupled by adhesive layers in spaces between the semiconductor dies; and
wherein the adhesive layers are recessed from the first electrical pads in the spaces between pairs of semiconductor dies.

### Claim 16

A system, comprising a chip package, wherein the chip package includes:
a processor;
a memory;
wherein the memory comprises a group of semiconductor dies arranged in a plank stack in an x direction, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces;
positive features mechanically coupled to the negative features on adjacent semiconductor dies, thereby aligning the semiconductor dies in the plank stack; and
an interposer plate electrically coupled to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction;
wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.

### Claim 17 (depends on 16)

The system of claim 16, wherein a first electrical pad on a given semiconductor die is included in the second negative feature recessed below one of the surfaces of the given semiconductor die.

### Claim 18 (depends on 17)

The system of claim 17, wherein the other negative feature is included in a dicing lane of the given semiconductor die.

### Claim 19 (depends on 16)

The system of claim 16, further comprising:
a mechanical-alignment plate; and
mechanical-alignment components, wherein the plank stack is mechanically coupled to the mechanical-alignment plate by the mechanical-alignment components, thereby facilitating alignment of the semiconductor dies in the plank stack; and
wherein the mechanical-alignment plate is mechanically coupled to the plank stack on an opposite face of the plank stack from the interposer plate.

### Claim 20

A method for fabricating a plank stack of semiconductor dies in an x direction, wherein the method comprises:
stacking the semiconductor dies along the x direction into the plank stack, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces;
while stacking the semiconductor dies, aligning the semiconductor dies in the plank stack by mechanically coupling positive features to the negative features on adjacent semiconductor dies; and
electrically coupling an interposer plate to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction;
wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.