# US 8,772,919 B2 · Image sensor package with trench insulator and fabrication method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,919 B2 - Document ID: US8772919B2 - Status: Granted - Kind: B2 - Application number: 12/753,519 - Filed: 2010-04-02 - Published: 2011-08-11 - Granted: 2014-07-08 - Earliest claimed: 2007-08-08 - Applicants: Wen-Cheng Chien; Wen-Ken Huang; Chien-Hung Liu; Joey Lai - Inventors: Wen-Cheng Chien; Wen-Ken Huang; Chien-Hung Liu; Joey Lai - Web page: https://patentgrep.com/patent/US8772919B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12} - H10F 39/804: {Containers or encapsulations} - H10W 72/0198: {batch processes} - H10W 72/90: Bond pads, in general - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad. ## Claims ### Claim 1 A chip package, comprising: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring coaxially surrounds an intermediate layer that comprises a material of the substrate coaxially surrounded by the trench, wherein the insulator ring, the intermediate layer and the trench form a coaxial structure directly below the conductive pad, wherein the insulator ring, the intermediate layer and the trench are coaxially located directly below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad through the coaxial structure. ### Claim 2 (depends on 1) The chip package as claimed in claim 1, further comprising a through hole formed in a region directly below the conductive pad and surrounded by the intermediate layer. ### Claim 3 (depends on 1) The chip package as claimed in claim 1, wherein the intermediate layer is cylindrical, and wherein the insulator ring coaxially surrounds the intermediate layer. ### Claim 4 (depends on 1) The chip package as claimed in claim 1, wherein the insulator ring comprises a material of silicon oxide, silicon nitride or silicon oxynitride. ### Claim 5 (depends on 1) The chip package as claimed in claim 1, wherein the intermediate layer comprises a semiconductor material. ### Claim 6 (depends on 1) The chip package as claimed in claim 1, wherein the intermediate layer comprises a multilayer structure. ### Claim 7 (depends on 6) The chip package as claimed in claim 6, wherein the multilayer structure comprises semiconductor materials, insulating materials, or combinations thereof. ### Claim 8 (depends on 6) The chip package as claimed in claim 6, wherein the multilayer structure comprises materials having a coefficient of thermal expansion between a coefficient of thermal expansion of the insulator ring and a coefficient of thermal expansion of the conductive layer. ### Claim 9 (depends on 1) The chip package as claimed in claim 1, wherein the intermediate layer comprises a heavily doped region, and the conductive layer is electrically connected to the conductive pad through the heavily doped region. ### Claim 10 (depends on 9) The chip package as claimed in claim 9, wherein the conductive layer extends into a portion of the heavily doped region. ### Claim 11 (depends on 1) The chip package as claimed in claim 1, further comprising a covering plate over the substrate; and a support member located between the covering plate and the substrate. ### Claim 12 (depends on 1) The chip package as claimed in claim 1, wherein the insulator ring coaxially surrounds both the intermediate layer and the conductive layer directly below the conductive pad. ### Claim 13 (depends on 2) The chip package as claimed in claim 2, wherein the top of the conductive layer extends into the through hole to physically contact the bottom of the conductive pad. ### Claim 14 (depends on 1) The chip package as claimed in claim 1, wherein the top of the conductive layer is located directly below the bottom of the conductive pad. ### Claim 15 (depends on 1) The chip package as claimed in claim 1, wherein the coaxial structure further comprises the conductive layer, wherein the conductive layer is coaxial to the intermediate layer and the insulator layer. ### Claim 16 (depends on 1) The chip package as claimed in claim 1, wherein within the coaxial structure directly below the conductive pad, a cylindrical surface of the insulator ring directly contacts a first cylindrical surface of the intermediate layer. ### Claim 17 (depends on 16) The chip package as claimed in claim 16, wherein within the coaxial structure directly below the conductive pad, a cylindrical surface of the conductive layer directly contacts a second cylindrical surface of the intermediate layer, wherein the first and second cylindrical surfaces of the intermediate layer are coaxial. ### Claim 18 (depends on 1) The chip package as claimed in claim 1, wherein the intermediate layer comprises a heavily doped region in contact with the bottom of the conductive pad, and the conductive layer is electrically connected to the conductive pad through the heavily doped region. ### Claim 19 A chip package, comprising: a substrate having a semiconductor device and a conductive pad supported thereon; and a coaxial structure in the substrate directly below the conductive pad, wherein said coaxial structure comprises an insulator ring and an intermediate layer comprising a material of the substrate coaxially disposed within the insulator ring, and wherein both the insulator ring and the intermediate layer are located directly below the conductive pad. ### Claim 20 (depends on 19) The chip package as claimed in claim 19, wherein in the coaxial structure further comprises a conductive layer electrically connected to the conductive pad through the coaxial structure. ### Claim 21 (depends on 20) The chip package as claimed in claim 20, wherein the insulator ring surrounds both the intermediate layer and the conductive layer. ### Claim 22 (depends on 21) The chip package as claimed in claim 21, wherein the insulator ring is coaxial to the intermediate layer and the conductive layer. ### Claim 23 (depends on 20) The chip package as claimed in claim 20, wherein the conductive layer is defined in a via defined along an axis of the coaxial structure. ### Claim 24 (depends on 19) The chip package as claimed in claim 19, wherein the intermediate layer comprises a heavily doped region, and the conductive layer is electrically connected to the conductive pad through the heavily doped region. ### Claim 25 (depends on 19) The chip package as claimed in claim 19, wherein the insulator ring continuously surrounds the intermediate layer to electrically insulate the intermediate layer from the substrate. ### Claim 26 A chip package, comprising: a substrate; a semiconductor device supported on the substrate; a plurality of conductive pads supported on the substrate; and a plurality of coaxial structures formed in the substrate, wherein each coaxial structure is located directly below a different one of the plurality of conductive pads, and wherein each coaxial structure comprises an insulator ring and an intermediate layer comprising a material of the substrate coaxially surrounded by the insulator ring.