# US 8,772,914 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,914 B2 - Document ID: US8772914B2 - Status: Granted - Kind: B2 - Application number: 13/741,879 - Filed: 2013-01-15 - Published: 2013-05-23 - Granted: 2014-07-08 - Earliest claimed: 2009-09-02 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Yasutaka Nakashiba; Kenta Ogawa - Web page: https://patentgrep.com/patent/US8772914B2 ## CPC - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 70/442: {of multiple leadframes in a single chip} - H10W 70/451: {Multilayered leadframes} - H10W 72/00: Interconnections or connectors in packages - H10W 74/01: Manufacture or treatment - H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling} - H10W 90/811: {Multiple chips on leadframes} - H10W 44/234: {Arrangements for impedance matching} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 72/073: {of die-attach connectors} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/075: {of bond wires} - H10W 72/30: Die-attach connectors - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/351: {Materials of die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/00: Package configurations - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/732: {between stacked chips} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. ## Claims ### Claim 1 A semiconductor device comprising: a chip mounting portion comprising a first upper surface that is an upper surface of the chip mounting portion and a first lower surface that is a lower surface of the chip mounting portion opposite to the first upper surface; a first chip comprising a first multilayer interconnect layer and a first inductor formed in the first multilayer interconnect layer; and a second chip comprising a second multilayer interconnect layer and a second inductor formed in the second multilayer interconnect layer, wherein the first chip comprises a rectangular first front surface comprising a first terminal formed thereon and a first back surface opposite to the first front surface, wherein the first chip is mounted over the chip mounting portion such that the first upper surface of the chip mounting portion is faced with the first back surface of the first chip, wherein the second chip comprises a rectangular second front surface comprising a second terminal formed thereon and a second back surface opposite to the second front surface, wherein the second chip is mounted over the first chip such that the first front surface of the first chip is faced with the second front surface of the second chip, wherein the first inductor and the second inductor are disposed such that the first inductor and the second inductor are overlapped with each other as viewed from a direction perpendicular to the first upper surface of the chip mounting portion, and wherein the second front surface of the second chip comprises an extension region that does not overlap with the first upper surface of the chip mounting portion as viewed from a direction perpendicular to the first upper surface of the chip mounting portion. ### Claim 2 (depends on 1) The semiconductor device as set forth in claim 1, wherein the first chip comprises a first side surface between the first front surface and the first back surface, wherein the second chip comprises a second side surface between the second front surface and the second back surface, wherein the chip mounting portion comprises a third side surface between the first upper surface and the first lower surface, the semiconductor device further comprising sealing resin sealing the first side surface of the first chip, the second side surface of the second chip and the third side surface of the chip mounting portion. ### Claim 3 (depends on 2) The semiconductor device as set forth in claim 2, further comprising a plurality of leads comprising a first lead and a second lead, wherein the first lead comprises a first end that is one end of the first lead disposed in the sealing resin and a second end that is the other end of the first lead extending outside from the sealing resin while the second lead comprises a third end that is one end of the second lead disposed in the sealing resin and a fourth end that is the other end of the second lead extending outside from the sealing resin, the semiconductor device further comprising a first wire through which the first end of the first lead and the first terminal are connected and a second wire through which the third end of the second lead and the second terminal are connected. ### Claim 4 (depends on 3) The semiconductor device as set forth in claim 3, wherein the first upper surface of the chip mounting portion comprises a first side and a second side faced with the first lead and the second lead respectively as viewed from a direction perpendicular to the first upper surface of the chip mounting portion, wherein a distance between the first lead and the first side is less than a distance between the second lead and the second side. ### Claim 5 (depends on 3) The semiconductor device as set forth in claim 3, wherein the first end of the first lead comprises a second upper surface that is an upper surface of the first end of the first lead and a second lower surface that is a lower surface of the first end of the first lead opposite to the second upper surface, wherein a distance between the second upper surface of the first lead and the first lower surface of the chip mounting portion is greater than a distance between the second lower surface of the first lead and the first lower surface of the chip mounting portion, wherein the third end of the second lead comprises a third upper surface that is an upper surface of the third end of the second lead and a third lower surface that is a lower surface of the third end of the second lead opposite to the third upper surface, wherein a distance between the third upper surface of the second lead and the first lower surface of the chip mounting portion is greater than a distance between the third lower surface of the second lead and the first lower surface of the chip mounting portion, and wherein the first wire is connected to the second upper surface of the first end of the first lead while the second wire is connected to the third lower surface of the third end of the second lead. ### Claim 6 (depends on 5) The semiconductor device as set forth in claim 5, wherein a distance between a plane comprising the first upper surface of the chip mounting portion and the second front surface of the second chip is greater than a distance between a plane comprising the first upper surface of the chip mounting portion and the third lower surface of the third end of the second lead. ### Claim 7 (depends on 1) The semiconductor device as set forth in claim 1, wherein the first chip comprises at least one of a transmission circuit and a reception circuit connected to the first inductor while the second chip comprises the other of a transmission circuit and a reception circuit connected to the second inductor. ### Claim 8 (depends on 1) The semiconductor device as set forth in claim 1, wherein the first inductor and the second inductor transmit or send an electric signal using induction coupling. ### Claim 9 (depends on 7) The semiconductor device as set forth in claim 7, wherein the first chip comprises a substrate, wherein the transmission circuit or the reception circuit comprises a transistor formed in the substrate. ### Claim 10 (depends on 1) The semiconductor device as set forth in claim 1, wherein a potential amplitude of an electric signal input into the first chip and a potential amplitude of an electric signal input into the second chip are different from each other. ### Claim 11 (depends on 1) The semiconductor device as set forth in claim 1, wherein a referential potential of an electric signal input into the first chip and a referential potential of an electric signal input into the second chip are different from each other. ### Claim 12 (depends on 1) The semiconductor device as set forth in claim 1, further comprising an insulating layer formed between the first front surface of the first chip and the second front surface of the second chip. ### Claim 13 (depends on 12) The semiconductor device as set forth in claim 12, further comprising a sealing resin sealing the first chip and the second chip, wherein a part of the first front surface of the first chip is covered by the insulating layer whereas the other part of the first front surface of the first chip is covered by the sealing resin. ### Claim 14 (depends on 12) The semiconductor device as set forth in claim 12, wherein the insulating layer has a thickness equal to or more than 10 μm and equal to or less than 100 μm. ### Claim 15 (depends on 12) The semiconductor device as set forth in claim 12, wherein the first chip further comprises a first insulating film formed between the insulating layer and the first inductor, and wherein the second chip further comprises a second insulating film formed between the insulating layer and the second inductor. ### Claim 16 (depends on 15) The semiconductor device as set forth in claim 15, wherein the first insulating film and the second insulating film comprise a polyimide, wherein the first chip further comprises a third insulating film comprising silicon and formed between the first insulating film and the first inductor, and wherein the second chip further comprises a fourth insulating film comprising silicon and formed between the second insulating film and the second inductor. ### Claim 17 (depends on 1) The semiconductor device as set forth in claim 1, further comprising: a sealing resin sealing the first chip and the second chip; and a plurality of leads comprising a first lead and a second lead, wherein the first lead comprises a first end that is one end of the first lead disposed in the sealing resin and a second end that is the other end of the first lead extending outside from the sealing resin while the second lead comprises a third end that is one end of the second lead disposed in the sealing resin and a fourth end that is the other end of the second lead extending outside from the sealing resin, the semiconductor device further comprising a first wire through which the first end of the first lead and the first terminal are connected and a second wire through which the third end of the second lead and the second terminal are connected, wherein the sealing resin, when viewed from a direction perpendicular to the first upper surface of the chip mounting portion, comprises a first sealing resin side, a second sealing resin side opposite to the first sealing resin side, a third sealing resin side between the first sealing resin side and the second sealing resin side and a fourth sealing resin side opposite to the third sealing resin side, and wherein the first lead crosses the first sealing resin side while the second lead crosses the second sealing resin side. ### Claim 18 (depends on 17) The semiconductor device as set forth in claim 17, wherein the second end of the first lead and the fourth end of the second lead are bent away from the first upper surface of the chip mounting potion. ### Claim 19 (depends on 17) The semiconductor device as set forth in claim 17, comprising no lead comprising one end formed in the sealing resin and the other end extending outside from the sealing resin and crossing the third sealing resin side or the fourth sealing resin side. ### Claim 20 (depends on 19) The semiconductor device as set forth in claim 19, further comprising a suspension lead extending between the chip mounting portion and any side of the sealing resin, wherein the suspension lead is formed between the chip mounting portion and at least any side of the first sealing resin side, the third resin sealing side and the fourth resin sealing side, and is not formed between the mounting portion and the second resin sealing side.