# US 8,772,913 B1 · Stiffened semiconductor die package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,913 B1 - Document ID: US8772913B1 - Status: Granted - Kind: B1 - Application number: 13/857,131 - Filed: 2013-04-04 - Granted: 2014-07-08 - Earliest claimed: 2013-04-04 - Assignees: Freescale Semiconductor, Inc. - Applicants: Kesvakumar V. C. Muniandy; Navas Khan Oratti Kalandar - Inventors: Kesvakumar V. C. Muniandy; Navas Khan Oratti Kalandar - Web page: https://patentgrep.com/patent/US8772913B1 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7448: {the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10P 72/7416: {used during dicing or grinding} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads. ## Claims ### Claim 1 A stiffened semiconductor die package, comprising: a semiconductor die including an integrated circuit, the semiconductor die having an active side with die bonding pads and an opposite inactive side; a conductive frame surrounding edges of the semiconductor die, wherein the conductive frame acts as a ground plane; a mold compound that covers the conductive frame and the semiconductor die; a thermally conductive sheet attached to the inactive side of the semiconductor die; and a dielectric support structure with external connector pads having solder deposits mounted thereto, the dielectric support structure being attached to the active side of the semiconductor die and wherein the external connector pads are electrically coupled to respective ones of the die bonding pads. ### Claim 2 (depends on 1) The stiffened semiconductor die package of claim 1, wherein at least one of the external connector pads is also electrically coupled to the conductive frame. ### Claim 3 (depends on 1) The stiffened semiconductor die package of claim 1, wherein a surface of the conductive frame is coplanar with a surface of the die bonding pads. ### Claim 4 (depends on 3) The stiffened semiconductor die package of claim 3, wherein the inactive side of the semiconductor die is coplanar with an aligned surface of the mold compound. ### Claim 5 (depends on 4) The stiffened semiconductor die package of claim 4, wherein the thermally conductive sheet is also attached to the aligned surface of the mold compound. ### Claim 6 (depends on 5) The stiffened semiconductor die package of claim 5, wherein the mold compound forms a rectangular frame around the edges of the semiconductor die. ### Claim 7 (depends on 6) The stiffened semiconductor die package of claim 6, wherein the mold compound is molded to the edges of the semiconductor die. ### Claim 8 (depends on 1) The stiffened semiconductor die package of claim 1, wherein the solder deposits form a grid array structure. ### Claim 9 (depends on 1) The stiffened semiconductor die package of claim 1, wherein the dielectric support structure is attached to the conductive frame thereby sandwiching conductive frame and mold compound between the thermally conductive sheet and the dielectric support structure.