# US 8,772,905 B2 · Integration of resistors and capacitors in charge trap memory device fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,905 B2 - Document ID: US8772905B2 - Status: Granted - Kind: B2 - Application number: 13/132,312 - Filed: 2008-12-30 - Published: 2011-10-13 - Granted: 2014-07-08 - Earliest claimed: 2008-12-30 - Assignees: Micron Technology, Inc. - Applicants: Umberto M. Meotto; Paolo Tessariol - Inventors: Umberto M. Meotto; Paolo Tessariol - Web page: https://patentgrep.com/patent/US8772905B2 ## CPC - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10B 43/30: characterised by the memory core region - H10B 43/40: characterised by the peripheral circuit region - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates. ## Claims ### Claim 1 A method of fabricating a semiconductor device structure, the method comprising: forming a dielectric layer of a charge trapping dielectric stack for a non-volatile memory cell, the dielectric layer being disposed over a first conductor peripheral to the memory cell; patterning the dielectric layer to expose a portion of the first conductor; forming a conductive material over the dielectric layer and in contact with the exposed portion of the first conductor; and patterning the conductive material to form circuitry including the first conductor and to form a portion of the memory cell, the patterning of the conductive material further comprising removing a portion of the conductive material to form a second conductor disposed over the first conductor, the second conductor being electrically isolated from a portion of the conductive material contacting the first conductor, the first conductor and the second conductor being dimensioned to form a capacitor. ### Claim 2 (depends on 1) The method of claim 1, wherein the first conductor is a patterned layer disposed over a semiconductor substrate or is a doped region of the semiconductor substrate. ### Claim 3 (depends on 1) The method of claim 1, wherein the dielectric layer is a charge trapping layer of the charge trapping dielectric stack. ### Claim 4 (depends on 1) The method of claim 1, wherein patterning the dielectric layer further comprises: forming, in the dielectric layer, a first contact opening and a second contact opening spaced apart from one another to expose two distinct regions of the first conductor. ### Claim 5 The method of 1, wherein patterning the conductive material further comprises retaining a second portion of the conductive material contacting the first conductor to form conductive heads of a resistor. ### Claim 6 (depends on 1) The method of claim 1, wherein the dielectric layer is a silicon nitride or a high-k dielectric having a dielectric constant greater than a silicon nitride and wherein the first conductor is a patterned poly-silicon or metal feature. ### Claim 7 (depends on 1) The method of claim 1, wherein the memory cell is a NAND memory cell. ### Claim 8 A semiconductor device structure, comprising: a memory cell region of a substrate, the memory cell region including a non-volatile charge trapping dielectric stack; a peripheral region of the substrate, the peripheral region including a dielectric layer of the non-volatile charge trapping dielectric stack disposed over a first conductor; circuitry formed from a conductive material including the first conductor to form a portion of the semiconductor device structure as a resistor element; and a second conductor disposed over the first conductor, the second conductor being electrically isolated from a portion of the conductive material contacting the first conductor, the first conductor and the second conductor being dimensioned to form a capacitor. ### Claim 9 (depends on 8) The semiconductor device structure of claim 8, wherein the dielectric layer is disposed over only a portion of the first conductor. ### Claim 10 (depends on 8) The semiconductor device structure of claim 8, wherein the first conductor is a patterned layer disposed over a semiconductor substrate or is a doped region of the semiconductor substrate. ### Claim 11 (depends on 8) The semiconductor device structure of claim 8, wherein the dielectric layer is a charge trapping layer of the charge trapping dielectric stack. ### Claim 12 (depends on 8) The semiconductor device structure of claim 8, further comprising: a first conductive contact and a second conductive contact disposed over the dielectric layer, wherein each of the first conductive contact and the second conductive contact is electrically coupled with a distinct portion of the first conductor. ### Claim 13 (depends on 12) The semiconductor device structure of claim 12, wherein a portion of the first conductor forms a resistor. ### Claim 14 (depends on 8) The semiconductor device structure of claim 8, wherein the dielectric layer is a silicon nitride or a high-k dielectric having a dielectric constant greater than the silicon nitride and wherein the first conductor is a patterned poly-silicon or a metal feature. ### Claim 15 A method of fabricating a semiconductor device structure, the method comprising: patterning a conductive layer into a transistor gate and at least one of a capacitor plate or a resistor in a peripheral region of the semiconductor device; depositing a dielectric layer as part of a non-volatile charge trapping dielectric stack of a memory cell in an array region of the semiconductor device; and patterning a portion of the dielectric layer disposed over the peripheral region to expose the entire transistor gate, but expose only a portion of the capacitor plate or expose only a portion of the resistor. ### Claim 16 (depends on 15) The method of claim 15, further comprising forming a conductive layer on the non-volatile charge trapping dielectric stack, on the transistor gate and in contact with the portion of the capacitor plate or resistor.