# US 8,772,889 B2 · Magnetic domain wall shift register memory device readout

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- Number: US 8,772,889 B2
- Document ID: US8772889B2
- Status: Granted
- Kind: B2
- Application number: 13/682,063
- Filed: 2012-11-20
- Published: 2014-05-22
- Granted: 2014-07-08
- Earliest claimed: 2012-11-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Michael C. Gaidis; Alexander J. Gaidis
- Web page: https://patentgrep.com/patent/US8772889B2

## CPC

- H10N 50/01: Manufacture or treatment
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 19/0808: {using magnetic domain propagation}
- H01F 10/3263: {the exchange coupling being symmetric, e.g. for dual spin valve, e.g. NiO/Co/Cu/Co/Cu/Co/NiO}
- H10N 50/10: Magnetoresistive devices
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 99/00: Subject matter not provided for in other groups of this subclass
- H01F 1/0072: {one dimensional, i.e. linear or dendritic nanostructures}
- H10D 62/121: {oriented parallel to substrates}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.

## Claims

### Claim 1

A memory device, comprising:
a first nanowire;
a second nanowire; and
a magnetic tunnel junction (MTJ) device coupling the first and second nanowires, the MTJ device disposed between the first and second nanowires, and wherein the MTJ device comprises a first MTJ disposed on the first nanowire, a second MTJ disposed on the second nanowire and a common reference layer disposed between the first and second MTJs.

### Claim 2 (depends on 1)

The memory device as claimed in claim 1 further comprising a readout transistor coupled to the common reference layer.

### Claim 3 (depends on 1)

The memory device as claimed in claim 1 further comprising a readout transistor coupled to at least one of the first and second nanowires.

### Claim 4 (depends on 1)

The memory device as claimed in claim 1 further comprising a shift transistor coupled to each of the first and second nanowires.

### Claim 5 (depends on 1)

The memory device as claimed in claim 1 further comprising a ground connector coupled to at least one of the first and second nanowires.

### Claim 6 (depends on 1)

The memory device as claimed in claim 1 further comprising a ground connector coupled to the first and second nanowires.

### Claim 7 (depends on 1)

The memory device as claimed in claim 1 wherein the MTJ device comprises:
a first MTJ disposed on the first nanowire;
a second MTJ disposed on the second nanowire;
a common reference layer coupled to the first and second MTJs.

### Claim 8 (depends on 7)

The memory device as claimed in claim 7 further comprising a readout transistor coupled to the common reference layer.

### Claim 9 (depends on 7)

The memory device as claimed in claim 7 further comprising a first shift transistor coupled to at least one of the first and second nanowires.

### Claim 10 (depends on 9)

The memory device as claimed in claim 9 further comprising a second shift transistor coupled to at least one of the first and second nanowires.