# US 8,772,882 B2 · Semiconductor device and method of manufacturing semiconductor device

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- Number: US 8,772,882 B2
- Document ID: US8772882B2
- Status: Granted
- Kind: B2
- Application number: 13/609,643
- Filed: 2012-09-11
- Published: 2013-01-03
- Granted: 2014-07-08
- Earliest claimed: 2010-07-28
- Assignees: Fujitsu Semiconductor Limited
- Applicants: Kazuhiko Takada
- Inventors: Kazuhiko Takada
- Web page: https://patentgrep.com/patent/US8772882B2

## CPC

- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/49: comprising different types of peripheral transistor
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

## Claims

### Claim 1

A semiconductor device comprising:
a device isolation film defining a device region formed in a semiconductor substrate;
a memory cell transistor including a first insulating film formed above the device region; a floating gate formed above the first insulating film and having a first width in a first direction; a second insulating film formed above the floating gate; and a control gate formed above the floating gate with the second insulating film interposed therebetween and extended in the first direction;
a third insulating film formed above the semiconductor substrate with the memory cell transistor formed, the third insulating film having a contact hole reaching down to the device region, the contact hole having a second width in the first direction;
a fourth insulating film formed on a inside wall of the contact hole;
a contact plug formed in the contact hole with the fourth insulating film formed; and
a bit line connected to the contact plug and extended in the second direction.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the second width is larger than the first width.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the device region has a third width in the first direction, which is smaller than the first width, and
an edge of the device region in the first direction is positioned in the contact hole.