# US 8,772,880 B2 · Semiconductor integrated circuit device

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- Number: US 8,772,880 B2
- Document ID: US8772880B2
- Status: Granted
- Kind: B2
- Application number: 13/500,636
- Filed: 2010-10-04
- Published: 2012-10-04
- Granted: 2014-07-08
- Earliest claimed: 2009-10-06
- Assignees: Hitachi, Ltd.
- Applicants: Koji Fukuda; Hiroki Yamashita
- Inventors: Koji Fukuda; Hiroki Yamashita
- Web page: https://patentgrep.com/patent/US8772880B2

## CPC

- H03K 19/00384: {in field effect transistor circuits}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 89/10: Integrated device layouts
- H10D 84/217: {of only conductor-insulator-semiconductor capacitors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising:
a common source region;
N (N≧1) first gate layers and M (M≧1) third gate layers arranged so as to extend in a first direction and align sequentially starting from the common source region toward a second direction which is orthogonal to the first direction;
N second gate layers and M fourth gate layers arranged so as to extend in the first direction and align sequentially starting from the common source region toward a third direction which is parallel, and opposite, to the second direction;
a first diffusion layer which is arranged between the N first gate layers and the M third gate layers and which serves as a shared diffusion layer between the N first gate layers and the M third gate layers;
a third diffusion layer which faces the first diffusion layer such that the M third gate layers are interposed therebetween;
a second diffusion layer which is arranged between the N second gate layers and the M fourth gate layers and which serves as a shared diffusion layer between the N second gate layers and the M fourth gate layers; and
a fourth diffusion layer which faces the second diffusion layer such that the M fourth gate layers are interposed therebetween, wherein
the N first gate layers are gate fingers of a first MIS transistor and take a first differential input signal as an input,
the N second gate layers are gate fingers of a second MIS transistor and take a second differential input signal as an input,
the first diffusion layer is a drain of the first MIS transistor,
the second diffusion layer is a drain of the second MIS transistor, and
both of the third and the fourth diffusion layers are unconnected.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device according to claim 1,
wherein, when a first voltage is applied to the third gate layer, a second voltage different from the first voltage is applied to the fourth gate layer.

### Claim 3 (depends on 1)

The semiconductor integrated circuit device according to claim 1, wherein
the semiconductor integrated circuit device can select a voltage to be applied to each of the M third gate layers and a voltage to be applied to each of the M fourth gate layers from among two or more voltage values for each layer.

### Claim 4 (depends on 1)

The semiconductor integrated circuit device according to claim 1, wherein
the N is an odd number.

### Claim 5

A semiconductor integrated circuit device comprising:
a first MIS transistor of a first conductive type to whose gate a first differential input signal is inputted;
a second MIS transistor of the first conductive type to whose gate a second differential input signal is inputted;
a plurality of third MIS transistors of the first conductive type whose source-drain paths are connected in series; and
a plurality of fourth MIS transistors of the first conductive type whose source-drain paths are connected in series, wherein
one end of a series connection path formed of the plurality of third MIS transistors is connected to a drain of the first MIS transistor and the other end thereof is unconnected, and
one end of a series connection path formed of the plurality of fourth MIS transistors is connected to a drain of the second MIS transistor and the other end thereof is unconnected.

### Claim 6 (depends on 5)

The semiconductor integrated circuit device according to claim 5, wherein
one of the plurality of third MIS transistors is a third A transistor whose source or drain is connected to the drain of the first MIS transistor,
one of the plurality of fourth MIS transistors is a fourth A transistor whose source or drain is connected to the drain of the second MIS transistor, and
the third A transistor and the fourth A transistor are controlled so that either one of them is turned on and the other is turned off.

### Claim 7 (depends on 6)

The semiconductor integrated circuit device according to claim 6, wherein
the semiconductor integrated circuit device can select and apply either a first gate voltage for the control to turn on or a second gate voltage for the control to turn off to each gate of the plurality of third MIS transistors and the plurality of fourth MIS transistors.

### Claim 8 (depends on 6)

The semiconductor integrated circuit device according to claim 6, wherein
the drain of the first MIS transistor and either the source or the drain of the third A transistor are formed of a common diffusion layer, and
the drain of the second MIS transistor and either the source or the drain of the fourth A transistor are formed of a common diffusion layer.

### Claim 9 (depends on 5)

The semiconductor integrated circuit device according to claim 5, wherein
each of the first and the second MIS transistors is configured of N gate fingers, the N being an odd number of three or larger, and
each gate length and each gate width of the plurality of third MIS transistors and the plurality of fourth MIS transistors are equal to a gate length and a gate width of each gate finger of the N gate fingers.

### Claim 10

A semiconductor integrated circuit device comprising:
first and second nodes;
a first MIS transistor of a first conductive type to whose gate a first differential input signal is inputted and whose drain is connected to the first node;
a second MIS transistor of the first conductive type to whose gate a second differential input signal is inputted, whose drain is connected to the second node, and whose source is commonly connected to a source of the first MIS transistor;
a plurality of third MIS transistors of the first conductive type whose source-drain paths are connected in series, one end of the series connection path is connected to the first node and the other end thereof is unconnected;
a plurality of fourth MIS transistors of the first conductive type whose source-drain paths are connected in series, one end of the series connection path is connected to the second node and the other end thereof is unconnected;
a fifth MIS transistor of the first conductive type for connecting the common source node of the first and the second MIS transistors to a first voltage when a clock signal is at a first logic level;
sixth and seventh MIS transistors for connecting the first and the second nodes to a second voltage when the clock signal is at a second logic level; and
a latch circuit unit for detecting which one of the first node and the second node is first changed from the second voltage to the first voltage in accordance with the differential input signals when the clock signal transits from the second logic level to the first logic level and latching information about the detection.

### Claim 11 (depends on 10)

The semiconductor integrated circuit device according to claim 10, wherein
one of the plurality of third MIS transistors is a third A transistor whose source or drain is connected to the first node,
one of the plurality of fourth MIS transistors is a fourth A transistor whose source or drain is connected to the second node, and
the third A transistor and the fourth A transistor are controlled so that either one of them is turned on and the other is turned off.

### Claim 12 (depends on 11)

The semiconductor integrated circuit device according to claim 11, wherein
the drain of the first MIS transistor and either the source or the drain of the third A transistor are formed of a common diffusion layer, and
the drain of the second MIS transistor and either the source or the drain of the fourth A transistor are formed of a common diffusion layer.

### Claim 13 (depends on 12)

The semiconductor integrated circuit device according to claim 12, wherein
each of the first and the second MIS transistors is configured of N gate fingers, the N being an odd number of three or larger, and
each gate length and each gate width of the plurality of third MIS transistors and the plurality of fourth MIS transistors are equal to a gate length and a gate width of each gate finger of the N gate fingers.

### Claim 14 (depends on 10)

The semiconductor integrated circuit device according to claim 10, wherein the latch circuit unit includes:
a first inverter circuit taking the first node as an input signal and outputting an inversion signal of the input signal to a third node;
a second inverter circuit taking the second node as an input signal and outputting an inversion signal of the input signal to a fourth node;
a CMOS-type latch circuit taking the third node and the fourth node as input signals and outputting the input signals to a fifth node and a sixth node; and
an SR latch circuit taking the fifth node and the sixth node as input signals and outputting the input signals to a seventh node and an eighth node, and the CMOS-type latch circuit includes:
an eighth MIS transistor of the first conductive type and a ninth MIS transistor of a second conductive type whose gates are connected to the third node;
a tenth MIS transistor of the first conductive type and an eleventh MIS transistor of the second conductive type whose gates are connected to the fourth node;
a twelfth MIS transistor of the first conductive type whose source is connected to a drain of the eighth MIS transistor and whose drain is connected to a drain of the ninth MIS transistor;
a thirteenth MIS transistor of the second conductive type whose source and drain are connected to a source and a drain of the ninth MIS transistor;
a fourteenth MIS transistor of the first conductive type whose source is connected to a drain of the tenth MIS transistor and whose drain is connected to a drain of the eleventh MIS transistor; and
a fifteenth MIS transistor of the second conductive type whose source and drain are connected to a source and a drain of the eleventh MIS transistor,
gates of the twelfth and the thirteenth MIS transistors and the drain of the fourteenth MIS transistor are connected to the fifth node, and
gates of the fourteenth and the fifteenth MIS transistors and the drain of the twelfth MIS transistor are connected to the sixth node.

### Claim 15

A semiconductor integrated circuit device comprising:
first and second nodes;
a first MIS transistor of a first conductive type to whose gate a first differential input signal is inputted and whose drain is connected to the first node;
a second MIS transistor of the first conductive type to whose gate a second differential input signal is inputted, whose drain is connected to the second node, and whose source is commonly connected to a source of the first MIS transistor;
a plurality of third MIS transistors of the first conductive type whose source-drain paths are connected in series, one end of the series connection path is connected to the first node and the other end thereof is unconnected;
a plurality of fourth MIS transistors of the first conductive type whose source-drain paths are connected in series, one end of the series connection path is connected to the second node and the other end thereof is unconnected;
a fifth MIS transistor of the first conductive type for connecting the common source node of the first and the second MIS transistors to a first voltage when a clock signal is at a first logic level;
sixth and seventh MIS transistors for connecting the first and the second nodes to a second voltage when the clock signal is at a second logic level; and
a latch circuit unit for detecting which one of the first node and the second node is first changed from the second voltage to the first voltage in accordance with the differential input signals when the clock signal transits from the second logic level to the first logic level and latching information about the detection, wherein
one of the plurality of third MIS transistors is a third A transistor whose source or drain is connected to the first node,
one of the plurality of fourth MIS transistors is a fourth A transistor whose source or drain is connected to the second node, and
the third A transistor and the fourth A transistor are controlled so that one of them is turned on and the other is turned off based on a latch data of the latch circuit unit.

### Claim 16 (depends on 15)

The semiconductor integrated circuit device according to claim 15, wherein
the drain of the first MIS transistor and either the source or the drain of the third A transistor are formed of a common diffusion layer, and
the drain of the second MIS transistor and either the source or the drain of the fourth A transistor are formed of a common diffusion layer.

### Claim 17 (depends on 16)

The semiconductor integrated circuit device according to claim 16, wherein
each of the first and the second MIS transistors is configured of N gate fingers, the N being an odd number of three or larger, and
each gate length and each gate width of the plurality of third MIS transistors and the plurality of fourth MIS transistors are equal to a gate length and a gate width of each gate finger of the N gate fingers.

### Claim 18 (depends on 15)

The semiconductor integrated circuit device according to claim 15, wherein the latch circuit unit includes:
a first inverter circuit taking the first node as an input signal and outputting an inversion signal of the input signal to a third node;
a second inverter circuit taking the second node as an input signal and outputting an inversion signal of the input signal to a fourth node;
a CMOS-type latch circuit taking the third node and the fourth node as input signals and outputting the input signals to a fifth node and a sixth node; and
an SR latch circuit taking the fifth node and the sixth node as input signals and outputting the input signals to a seventh node and an eighth node, and
the CMOS-type latch circuit includes:
an eighth MIS transistor of the first conductive type and a ninth MIS transistor of a second conductive type whose gates are connected to the third node;
a tenth MIS transistor of the first conductive type and an eleventh MIS transistor of the second conductive type whose gates are connected to the fourth node;
a twelfth MIS transistor of the first conductive type whose source is connected to a drain of the eighth MIS transistor and whose drain is connected to a drain of the ninth MIS transistor;
a thirteenth MIS transistor of the second conductive type whose source and drain are connected to a source and a drain of the ninth MIS transistor;
a fourteenth MIS transistor of the first conductive type whose source is connected to a drain of the tenth MIS transistor and whose drain is connected to a drain of the eleventh MIS transistor; and
a fifteenth MIS transistor of the second conductive type whose source and drain are connected to a source and a drain of the eleventh MIS transistor,
gates of the twelfth and the thirteenth MIS transistors and the drain of the fourteenth MIS transistor are connected to the fifth node, and
gates of the fourteenth and the fifteenth MIS transistors and the drain of the twelfth MIS transistor are connected to the sixth node.