# US 8,772,879 B2 · Electronic component comprising a number of MOSFET transistors and manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,879 B2 - Document ID: US8772879B2 - Status: Granted - Kind: B2 - Application number: 13/488,038 - Filed: 2012-06-04 - Published: 2012-12-13 - Granted: 2014-07-08 - Earliest claimed: 2011-06-07 - Assignees: STMicroelectronics (Crolles 2) SAS - Applicants: Jean-Luc Huguenin; Stéphane Monfray - Inventors: Jean-Luc Huguenin; Stéphane Monfray - Web page: https://patentgrep.com/patent/US8772879B2 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 84/014: {the gate conductors having different materials or different implants} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 30/0212: {using self-aligned silicidation} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electronic component including a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, wherein each transistor includes a gate that has two electrodes, namely a first electrode embedded inside the substrate where the channel of the transistor is defined and a second upper electrode located above the substrate facing buried electrode relative to channel and separated from said channel by a layer of dielectric material and wherein the embedded electrodes of all the transistors are formed by an identical material, the upper electrodes having a layer that is in contact with the dielectric material which is formed by materials that differ from one subset of transistors to another. ## Claims ### Claim 1 Electronic component comprising a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, wherein each transistor has two gates, namely a first gate embedded in the substrate where the channel of the transistor is defined and separated from said channel by a layer of dielectric material and a second upper gate located above the substrate and facing buried gate relative to channel, with the upper gates having a layer that is in contact with a single stack of dielectric material which is formed by materials that differ from one transistor to another and wherein the buried gates of the set of transistors are formed by an identical material. ### Claim 2 (depends on 1) Component as claimed in claim 1, wherein the transistors are divided up into three distinct subsets. ### Claim 3 (depends on 1) Component as claimed in claim 1, wherein the upper gates are formed by stacking layers of different materials, with the number of layers differing from one subset of transistors to another. ### Claim 4 (depends on 1) Component as claimed in claim 1, wherein the material of the buried gates is different from the materials of the upper gates of all the subsets of transistors. ### Claim 5 (depends on 1) Component as claimed in claim 1, wherein the material of the buried gates is part of the group of materials used in order to form the upper gates. ### Claim 6 (depends on 1) Component as claimed in claim 1, wherein, for NMOS type transistors and a first subset, the layer of the upper gate that is in contact with the layer of dielectric material is a material chosen from a group comprising aluminum and molybdenum. ### Claim 7 (depends on 1) Component as claimed in claim 1, wherein, for NMOS type transistors and a second subset, the layer of the upper gate that is in contact with the layer of dielectric material is a material chosen from a group comprising tantalum nitride and titanium nitride. ### Claim 8 (depends on 1) Component as claimed in claim 1, wherein, for NMOS type transistors and a third subset, the layer of the upper gate that is in contact with the layer of dielectric material is a material chosen from a group comprising titanium nitride and cobalt disilicide (CoSi2). ### Claim 9 (depends on 1) Component as claimed in claim 1, wherein, for PMOS type transistors and a first subset, the layer of the upper gate that is in contact with the layer of dielectric material is a material chosen from a group comprising nickel, gold and platinum. ### Claim 10 (depends on 1) Component as claimed in claim 1, wherein, for PMOS type transistors and a second subset, the layer of the upper gate that is in contact with the layer of dielectric material is a material chosen from a group comprising silicon and nickel. ### Claim 11 (depends on 1) Component as claimed in claim 1, wherein, for PMOS type transistors and a third subset, the layer of the upper gate that is in contact with the layer of dielectric material is a material chosen from a group comprising titanium nitride and cobalt disilicide (CoSi2). ### Claim 12 Method for manufacturing a number of insulated-gate field effect transistors on a semiconductor substrate which involves: making a recessed opening in the substrate located underneath the channel of each transistor; above each channel, producing upper gate structures having at least two types of metallic materials defining at least two subsets of transistors that have different threshold voltages; and depositing, in the recessed openings, a dielectric material then filling the openings with an identical metallic material for all the transistors in order to define a buried gate structure. ### Claim 13 (depends on 12) Method as claimed in claim 12, wherein one deposits the metallic materials for the upper gate structures by successively depositing different metal layers with the number of deposited layers defining the subset to which the transistor belongs. ### Claim 14 (depends on 12) Method as claimed in claim 12, wherein: one forms the openings then one fills them with a sacrificial material; one produces the upper gate structures, including the metallic materials; one removes the sacrificial material from the openings; one fills the recessed openings with a metallic material. ### Claim 15 (depends on 12) Method as claimed in claim 12, wherein: one forms upper gate structures by using a sacrificial material instead of electrodes; one produces recessed openings; one removes the sacrificial material from the upper gate structures; one deposits the metallic materials of the upper gate structures; one fills the recessed openings with a metallic material. ### Claim 16 (depends on 12) Method as claimed in claim 12, wherein: one produces the recessed openings and the areas that form the locations of the upper gate structures at the same time; one deposits the metallic materials of the upper gate structures in said areas; one fills the recessed openings with a metallic material.